Sonic Zhang's patches are too big for the mailing list so I have stored
them in ftp://oss.sgi.com//projects/kdb/download/v4.0/kdb-smphdr* and
extracted the start of the mail for the list.
From: "Zhang, Sonic" <[EMAIL PROTECTED]>
Hi,
I have enhanced my last patch for hardware debug register on
ia64 to support different hard breakpoints on different CPU.
And I also integrated this patch with former patch on i386 to
generate a complete version.
With this patch, you can:
1. Create, delete and use hardware instruction and data
breakpoints on ia64 architecture, such as Itanium / Itanium 2.
2. Create local and global hardware breakpoints concurrent.
3. Create different local hardware breakpoints on different
CPUs. All debug registers of each CPU can be fully utilized,
no waste.
Sample:
CPU1 CPU2
--------------------------------------------
dr0 (local) bp1 bp5
dr1 (global) bp2 bp2
dr2 (global) bp3 bp3
dr3 (local) bp4 bp6
Current known issues in my patch:
1. The IP and instruction debug registers on ia64 always point
to a bundle of 3 instructions, while the psr.id bit is
defined to resume 1 instruction in a bundle. That means the
instruction stream traps into the same hardware breakpoint
continuously for 3 times before the IP changes to a large
address.
2. I have trouble to let the psr.dd bit work for ia64 hardware
data breakpoint. This problem is under investigation. Could
you give me some ideas?
Please take a look at the attachment. It is based on the latest KDB v4.0.
Thank you.
*************************************
Sonic Zhang
Software Engineer
Intel China Software Lab
Tel: 021-52574545-1667
iNet: 8-752-1667
*************************************
