https://bugs.kde.org/show_bug.cgi?id=503098
Bug ID: 503098
Summary: Incorrect NAN-boxing for float registers in RISC-V
Classification: Developer tools
Product: valgrind
Version: unspecified
Platform: Other
OS: Linux
Status: REPORTED
Severity: normal
Priority: NOR
Component: vex
Assignee: [email protected]
Reporter: [email protected]
Target Milestone: ---
Created attachment 180473
--> https://bugs.kde.org/attachment.cgi?id=180473&action=edit
riscv64: Fix nan-boxing for single-precision calculations
Float arithmetic instructions check input registers. If any of input registers
is not NAN-boxed, this instruction treats it as canonical NAN. Here is a line
from the RISC-V unprivileged specification:
```
NaN Boxing of Narrower Values
...
Apart from transfer operations described in the previous paragraph, all other
floating-point operations on narrower-bit operations (n<FLEN) check if the
input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If
so, the n least-significant bits of the input are used as the input value,
otherwise the input value is treated as an n-bit canonical NaN.
```
Currently, as we use FLW to get a float register, the register is always
correctly NaN-boxed, which results in a wrong operation result.
Attached file is the patch that fixes this behavior.
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