https://bugs.kde.org/show_bug.cgi?id=509157
--- Comment #5 from CF Bolz-Tereick <[email protected]> --- Thanks for clarifying, Florian! Indeed, looking at aarch64 and amd64, they both explicitly introduce and-instructions to mask off the higher bits. We can prepare a patch to introduce the same masks in the RISC-V code, and maybe also add a comment about the intended semantics of VEX shifts. However, I am not sure what kind of test we should usefully add? -- You are receiving this mail because: You are watching all bug changes.
