--- Comment #16 from Julian Seward <> ---
(In reply to Maran Pakkirisamy from comment #8)


I was studying this bug and your fix, so as to see how to apply it to ARM.
I have a question:

> With the update, only step 3 is changed.
> [..]
> c) (a and b failed). Execute SC under CAS. That is, store will be performed
> if LLdata (saved when LL was executed) is same as SCdata (the current value
> at mem). And this step is performed atomically using CAS. This is the
> significant part of the change from the initial proposal. 

Your implementation ignores whether the CAS was successful or not.

Should it instead cause the SC to fail (set rt to zero) if the CAS fails?

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