https://bugs.kde.org/show_bug.cgi?id=384584
Bug ID: 384584
Summary: list first callee saved registers for AMD64, X86, and
PPC architectures
Product: valgrind
Version: 3.14 SVN
Platform: Compiled Sources
OS: Linux
Status: UNCONFIRMED
Severity: normal
Priority: NOR
Component: vex
Assignee: [email protected]
Reporter: [email protected]
Target Milestone: ---
For a particular architecture, VEX structure RRegUniverse describes real
registers available to the register allocator and also those used only
internally by the backend.
For many architectures, such as ARM32, ARM64, MIPS, the callee saved registers
are listed first in RRegUniverse's allocatable section.
However AMD64, X86 and PPC have caller saved registers first.
A small performance improvement for both VEX register allocator v2 and v3 has
been observed if the callee saved registers are listed first.
Register allocator is more likely to pick the callee saved register first and
therefore does not need to spill them when calling helper functions.
Measuring Memcheck on perf/bz2, instruction count:
amd64 (Intel i5):
~~~~~~~~~~~~~~~~~
v2 baseline: 45,192 M total; 208 M register allocator
v2 reorder: 45,183 M total; 205 M register allocator
v3 baseline: 45,112 M total; 167 M register allocator
v3 reorder: 45,094 M total; 165 M register allocator
ppc (power8 le):
~~~~~~~~~~~~~~~~
v2 baseline: 61,983 M total; 397 M register allocator
v2 reorder: 61,970 M total; 376 M register allocator
v3 baseline: 61,939 M total; 348.6 M register allocator
v3 reorder: 61,909 M total; 347.9 M register allocator
It can be seen that v3 benefits more than v2 from the reordering.
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