--- Comment #9 from Julian Seward <> ---
(In reply to Daniel Lehman from comment #8)
> Created attachment 119759 [details]
> iretq implementation
> updated version of the iretq implementation i included in the tarball in

Daniel, all, sorry to have been so slow looking at this.  Thank you
for the patch.

The patch ignores the new values for %CS and %SS, which seems reasonable
to me, given that Vex doesn't model segment registers on x86_64 anyway
(per comment above dis_mov_S_E() in guest_amd64_toIR.c).

However, afaics, the patch also ignores the new value for %rflags.d, which
iirc is the string-operation direction flag.  We do need to restore that in
order that any pending string operations continue in the right direction,
I think.  See the implementation for POPF in that same file, for how to
set it.  The Intel docs for IRETQ have this in a couple of places:

    EFLAGS (CF, PF, AF, ZF, SF, TF, DF, OF, NT) ← tempEFLAGS;

which is why I think at least D should be restored.  I notice that
Vex also models the ID and AC flags (see, again, the POPF implementation)
but from the Intel docs it's not clear to me whether these also need
to be restoired from 'tempEFLAGS' above.

You are receiving this mail because:
You are watching all bug changes.

Reply via email to