** Changed in: linux (Ubuntu Groovy)
Status: In Progress => Fix Committed
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https://bugs.launchpad.net/bugs/1910965
Title:
riscv: backport support for SiFive Unmatched
Status in linux package in Ubuntu:
In Progress
Status in linux source package in Focal:
New
Status in linux source package in Groovy:
Fix Committed
Status in linux source package in Hirsute:
In Progress
Bug description:
== SRU Justifcation Groovy/RISCV ==
The SiFive HiFive Unmatched board should be supported as well as the current
Unleashed. There are various upstream commits for this support and some misc
fixes for the Unleashed and Unmatched that are required for this
board support.
== The fix(es) ==
The following changes since commit
7295e646e91b648b7f45b4f36eba14bfe59dd3f6:
UBUNTU: Ubuntu-riscv-5.8.0-13.15 (2020-12-15 10:33:23 +0100)
are available in the Git repository at:
https://git.launchpad.net/~colin-king/+git/ubuntu-riscv-groovy
for you to fetch changes up to
86de0730500269fee8b71fcb1be29193455c3be7:
UBUNTU: [Config] Align configs with Unleashed defconfigs (2021-01-11
09:37:13 +0000)
----------------------------------------------------------------
Colin Ian King (1):
UBUNTU: [Config] Align configs with Unleashed defconfigs
David Abdurachmanov (5):
PCI: microsemi: Add host driver for Microsemi PCIe controller
Microsemi PCIe expansion board DT entry.
HACK: Revert "of/device: Really only set bus DMA mask when appropriate"
SiFive Unleashed CPUFreq
SiFive HiFive Unleashed: Add PWM LEDs (D1, D2, D3, D4)
Greentime Hu (2):
irqchip/sifive-plic: Fix broken irq_set_affinity() callback
irqchip/sifive-plic: Fix getting wrong chip_data when interrupt is
hierarchy
Pragnesh Patel (1):
clk: sifive: Add clock enable and disable ops
Rob Herring (2):
dt-bindings: More whitespace clean-ups in schema files
dt-bindings: Explicitly allow additional properties in board/SoC schemas
Sagar Kadam (2):
dt-bindings: riscv: sifive-l2-cache: convert bindings to json-schema
dt-bindings: riscv: convert pwm bindings to json-schema
Sagar Shrikant Kadam (1):
i2c: ocores: fix polling mode workaround on FU540-C000 SoC
Yash Shah (6):
RISC-V: Update l2 cache DT documentation to add support for SiFive FU740
RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740
dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
riscv: dts: add initial support for the SiFive FU740-C000 SoC
dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched
board
riscv: dts: add initial board data for the SiFive HiFive Unmatched
Zong Li (5):
clk: sifive: Extract prci core to common base
clk: sifive: Use common name for prci configuration
clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
clk: sifive: Fix the wrong bit field shift
dt-bindings: fu740: prci: add YAML documentation for the FU740 PRCI
Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml | 60 ++++
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 +-
Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 6 +-
Documentation/devicetree/bindings/pwm/pwm-sifive.txt | 33 ---
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 72 +++++
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +
Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt | 51 ----
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 127
+++++++++
Documentation/devicetree/bindings/riscv/sifive.yaml | 20 +-
Documentation/devicetree/bindings/serial/sifive-serial.yaml | 4 +-
Documentation/devicetree/bindings/spi/spi-sifive.yaml | 10 +-
arch/riscv/Kconfig | 8 +
arch/riscv/Kconfig.socs | 2 +-
arch/riscv/boot/dts/sifive/Makefile | 3 +-
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
+++++++++++++++++++
arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts | 28 ++
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 66 +++++
arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253
+++++++++++++++++
arch/riscv/configs/defconfig | 5 +
debian.riscv/config/annotations | 17 +-
debian.riscv/config/config.common.ubuntu | 47 +--
drivers/clk/sifive/Kconfig | 8 +-
drivers/clk/sifive/Makefile | 2 +-
drivers/clk/sifive/fu540-prci.c | 599
++-------------------------------------
drivers/clk/sifive/fu540-prci.h | 21 ++
drivers/clk/sifive/fu740-prci.c | 123 ++++++++
drivers/clk/sifive/fu740-prci.h | 21 ++
drivers/clk/sifive/sifive-prci.c | 574
+++++++++++++++++++++++++++++++++++++
drivers/clk/sifive/sifive-prci.h | 299
++++++++++++++++++++
drivers/i2c/busses/i2c-ocores.c | 23 +-
drivers/irqchip/irq-sifive-plic.c | 10 +-
drivers/of/device.c | 4 +-
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-microsemi.c | 753
+++++++++++++++++++++++++++++++++++++++++++++++++
drivers/soc/sifive/sifive_l2_cache.c | 49 +++-
include/dt-bindings/clock/sifive-fu740-prci.h | 23 ++
38 files changed, 2906 insertions(+), 732 deletions(-)
create mode 100644
Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml
delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
delete mode 100644
Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
create mode 100644
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
create mode 100644
arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
create mode 100644 drivers/clk/sifive/fu540-prci.h
create mode 100644 drivers/clk/sifive/fu740-prci.c
create mode 100644 drivers/clk/sifive/fu740-prci.h
create mode 100644 drivers/clk/sifive/sifive-prci.c
create mode 100644 drivers/clk/sifive/sifive-prci.h
create mode 100644 drivers/pci/controller/pcie-microsemi.c
create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h
The RISC-V configs have also been re-aligned to match the RISC-V
Unleashed/Unmatched defconfig for improved clock and power stability and to fix
some weird clock/scheduling random RCU timeouts and hangs during heavy load on
slow backing store I/O at boot time.
== Test Case ==
Build ubuntu 5.8 risc kernel with these patches. QEMU and RISC-V
Unleashed and Unmatched should boot and be rebootable with this fixes.
Tested also with stress-ng and a network uptime ping test for 48
hours.
== Where problems could occur ==
Several places:
1. Clocks - IRQ and clock handling has been modified, so potential for random
timing behaviour changes.
2. CONFIG changes - now aligning the clock, scheduling and power config
settings to the defconfigs for RISC-V unleashed. This does improve stability on
the Ubuntu boots and reboots, but may have unforeseen side effects.
3. CPU affinity fixes should improve some historical SMP problems but may
uncover other SMP issues.
4. Some of these patches are still not upstream, so there may be some
question to their unreviewed quality.
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