** Description changed: [Impact] - * Some 4K monitors can not display as maximum resolution from i915 + * Some 4K monitors can not display as maximum resolution from i915 graphic. - * In some 4k monitors, it's support higher pixel clock + * In some 4k monitors, it's support higher pixel clock The following is the case I have: Modeline "Mode 0" 533.25 3840 3888 3920 4000 2160 2163 2168 2222 +hsync -vsync Which will be dropped because the mode rate is greater than i915 maximum data rate. kernel: [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 kernel: [drm:drm_mode_prune_invalid [drm]] Not using 3840x2160 mode: CLOCK_HIGH The BDB version of Intel vBIOS is 237 kernel: i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT signature "$VBT TIGERLAKE ", BDB version 237 In old i915 parsing rule (for greater than v216), the common rate is decoded as 16200 kernel: i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000 Since the Intel updated the parsing rule (for greater then 230). the common rate is up to 540000 kernel: i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, - 540000 + 540000 There are 4 lanes support. - i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:184:DP-2] Link + i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:184:DP-2] Link Training passed at link rate = 162000, lane count = 4, at DPRX In this monitor, the max rate (max_link_clock * max_lanes) is: 162000 * 4 = 648000 # if using old parsing rule (> 210) - 540000 * 4 = 2160000 # if using updated parsing rule (> 230) + 540000 * 4 = 2160000 # if using updated parsing rule (> 230) the maximum mode rate is DIV_ROUND_UP(pixel_clock * bpp, 8); the bpp here is minimum bpp, which is 6 * 3 = 18 ... - max bpc: 12 - range: (6, 12) + max bpc: 12 + range: (6, 12) ... thus: 533250 * 18 + 8 - 1 / 8 = 1199813 # this is maximum mode rate of this monitor. - Therefore, we need to use the updated parsing table (intel BDB table - version > 230) for supporting high pixel clock monitors. - + [Fix] + It needs to use the updated parsing table (intel BDB table version > 230) for supporting high pixel clock monitors. [Test Plan] - * Steps to reproduce - 1. Connect a high pixel clock monitor (533KHz in my case) to i915 graphic which vbios version is v237 (In my case: - ModelName "U2879G6" - VendorName "AOC" + * Steps to reproduce + 1. Connect a high pixel clock monitor (533KHz in my case) to i915 graphic which vbios version is v237 (In my case: + ModelName "U2879G6" + VendorName "AOC" - 2. Check the display setting, expect a 3840*2160*60Hz option but there + 2. Check the display setting, expect a 3840*2160*60Hz option but there is not 3840*2160*60Hz option. - * if upgrade drm debugging level then you will see the modeline be dropped because of high clock. + * if upgrade drm debugging level then you will see the modeline be dropped because of high clock. kernel: [drm:drm_mode_prune_invalid [drm]] Not using 3840x2160 mode: CLOCK_HIGH - * after applying the change, the resolution work good. + * after applying the change, the resolution work good. [Where problems could occur] - * This change considered the backward compatibility, which will check + * This change considered the backward compatibility, which will check the BDB version before applying different parsing rule. - * From software perspective, the monitor will show nothing if Intel + * From software perspective, the monitor will show nothing if Intel vBIOS using BDB > 230 with undefined dp_max_link_rate field. - * Otherwise, it looks quite ok. + * Otherwise, it looks quite ok.
** Description changed: [Impact] * Some 4K monitors can not display as maximum resolution from i915 graphic. * In some 4k monitors, it's support higher pixel clock The following is the case I have: Modeline "Mode 0" 533.25 3840 3888 3920 4000 2160 2163 2168 2222 +hsync -vsync Which will be dropped because the mode rate is greater than i915 maximum data rate. kernel: [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 kernel: [drm:drm_mode_prune_invalid [drm]] Not using 3840x2160 mode: CLOCK_HIGH The BDB version of Intel vBIOS is 237 kernel: i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT signature "$VBT TIGERLAKE ", BDB version 237 In old i915 parsing rule (for greater than v216), the common rate is decoded as 16200 kernel: i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000 Since the Intel updated the parsing rule (for greater then 230). the common rate is up to 540000 kernel: i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 There are 4 lanes support. i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:184:DP-2] Link Training passed at link rate = 162000, lane count = 4, at DPRX In this monitor, the max rate (max_link_clock * max_lanes) is: 162000 * 4 = 648000 # if using old parsing rule (> 210) 540000 * 4 = 2160000 # if using updated parsing rule (> 230) the maximum mode rate is DIV_ROUND_UP(pixel_clock * bpp, 8); the bpp here is minimum bpp, which is 6 * 3 = 18 ... max bpc: 12 range: (6, 12) ... thus: 533250 * 18 + 8 - 1 / 8 = 1199813 # this is maximum mode rate of this monitor. [Fix] - It needs to use the updated parsing table (intel BDB table version > 230) for supporting high pixel clock monitors. + + * It needs to use the updated parsing table (intel BDB table version > + 230) for supporting high pixel clock monitors. [Test Plan] * Steps to reproduce 1. Connect a high pixel clock monitor (533KHz in my case) to i915 graphic which vbios version is v237 (In my case: ModelName "U2879G6" VendorName "AOC" 2. Check the display setting, expect a 3840*2160*60Hz option but there is not 3840*2160*60Hz option. * if upgrade drm debugging level then you will see the modeline be dropped because of high clock. kernel: [drm:drm_mode_prune_invalid [drm]] Not using 3840x2160 mode: CLOCK_HIGH * after applying the change, the resolution work good. [Where problems could occur] * This change considered the backward compatibility, which will check the BDB version before applying different parsing rule. * From software perspective, the monitor will show nothing if Intel vBIOS using BDB > 230 with undefined dp_max_link_rate field. * Otherwise, it looks quite ok. -- You received this bug notification because you are a member of Kernel Packages, which is subscribed to linux in Ubuntu. https://bugs.launchpad.net/bugs/1922372 Title: i915 doesn't support some high pixel clock 4k * 60Hz monitors Status in OEM Priority Project: Triaged Status in linux package in Ubuntu: Incomplete Bug description: [Impact] * Some 4K monitors can not display as maximum resolution from i915 graphic. * In some 4k monitors, it's support higher pixel clock The following is the case I have: Modeline "Mode 0" 533.25 3840 3888 3920 4000 2160 2163 2168 2222 +hsync -vsync Which will be dropped because the mode rate is greater than i915 maximum data rate. kernel: [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9 kernel: [drm:drm_mode_prune_invalid [drm]] Not using 3840x2160 mode: CLOCK_HIGH The BDB version of Intel vBIOS is 237 kernel: i915 0000:00:02.0: [drm:intel_bios_init [i915]] VBT signature "$VBT TIGERLAKE ", BDB version 237 In old i915 parsing rule (for greater than v216), the common rate is decoded as 16200 kernel: i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000 Since the Intel updated the parsing rule (for greater then 230). the common rate is up to 540000 kernel: i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 There are 4 lanes support. i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:184:DP-2] Link Training passed at link rate = 162000, lane count = 4, at DPRX In this monitor, the max rate (max_link_clock * max_lanes) is: 162000 * 4 = 648000 # if using old parsing rule (> 210) 540000 * 4 = 2160000 # if using updated parsing rule (> 230) the maximum mode rate is DIV_ROUND_UP(pixel_clock * bpp, 8); the bpp here is minimum bpp, which is 6 * 3 = 18 ... max bpc: 12 range: (6, 12) ... thus: 533250 * 18 + 8 - 1 / 8 = 1199813 # this is maximum mode rate of this monitor. [Fix] * It needs to use the updated parsing table (intel BDB table version > 230) for supporting high pixel clock monitors. [Test Plan] * Steps to reproduce 1. Connect a high pixel clock monitor (533KHz in my case) to i915 graphic which vbios version is v237 (In my case: ModelName "U2879G6" VendorName "AOC" 2. Check the display setting, expect a 3840*2160*60Hz option but there is not 3840*2160*60Hz option. * if upgrade drm debugging level then you will see the modeline be dropped because of high clock. kernel: [drm:drm_mode_prune_invalid [drm]] Not using 3840x2160 mode: CLOCK_HIGH * after applying the change, the resolution work good. [Where problems could occur] * This change considered the backward compatibility, which will check the BDB version before applying different parsing rule. * From software perspective, the monitor will show nothing if Intel vBIOS using BDB > 230 with undefined dp_max_link_rate field. * Otherwise, it looks quite ok. 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