Author: tbm
Date: Sun Jan 29 23:16:49 2006
New Revision: 5624

Added:
   
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/24_cobalt_cache_line.dpatch
   (contents, props changed)
   
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/29_cobalt_tulip2.dpatch
   (contents, props changed)
Modified:
   
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/config/mipsel/r5k-cobalt
   dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/00list
Log:
more cobalt fixes by phd


Modified: 
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/config/mipsel/r5k-cobalt
==============================================================================
--- 
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/config/mipsel/r5k-cobalt
        (original)
+++ 
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/config/mipsel/r5k-cobalt
        Sun Jan 29 23:16:49 2006
@@ -683,6 +683,7 @@
 CONFIG_DE2104X=y
 CONFIG_TULIP=y
 CONFIG_TULIP_MWI=y
+CONFIG_TULIP_MWI_DC21143=y
 CONFIG_TULIP_MMIO=y
 # CONFIG_TULIP_NAPI is not set
 # CONFIG_DE4X5 is not set

Modified: 
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/00list
==============================================================================
--- dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/00list  
(original)
+++ dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/00list  
Sun Jan 29 23:16:49 2006
@@ -10,10 +10,12 @@
 21_ip30.dpatch
 22_fix_cmdline.dpatch
 23_ip30_physaddr.dpatch
+24_cobalt_cache_line.dpatch
 25_cobalt-network.dpatch
 26_cobalt-ll-sc.dpatch
 27_cobalt-def_fix.dpatch
 28_cobalt_ide.dpatch
+29_cobalt_tulip2.dpatch
 30_sb1_pci_fix.dpatch
 31_sb1_remove_debug.dpatch
 32_sb1_probe_ide.dpatch

Added: 
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/24_cobalt_cache_line.dpatch
==============================================================================
--- (empty file)
+++ 
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/24_cobalt_cache_line.dpatch
     Sun Jan 29 23:16:49 2006
@@ -0,0 +1,50 @@
+#! /bin/sh -e
+## 24_cobalt_cache_line.dpatch by Peter Horton
+
+## DP: Fix Cobalt PCI cache line sizes
+
+if [ $# -lt 1 ]; then
+    echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+    exit 1
+fi
+
+[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts
+patch_opts="${patch_opts:--f --no-backup-if-mismatch} ${2:+-d $2}"
+
+case "$1" in
+    -patch) patch -p1 ${patch_opts} < $0;;
+    -unpatch) patch -R -p1 ${patch_opts} < $0;;
+    *)
+        echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+        exit 1;;
+esac
+
+exit 0
+
+Correct cache line sizes.
+
+P.
+
+Index: linux.git/arch/mips/pci/fixup-cobalt.c
+===================================================================
+--- linux.git.orig/arch/mips/pci/fixup-cobalt.c        2006-01-29 
12:35:50.000000000 +0000
++++ linux.git/arch/mips/pci/fixup-cobalt.c     2006-01-29 12:36:59.000000000 
+0000
+@@ -52,7 +52,7 @@
+       pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
+       if (lt < 64)
+               pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
+-      pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
++      pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
+ }
+ 
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
+@@ -69,7 +69,7 @@
+        * host bridge.
+        */
+       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
+-      pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
++      pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
+ 
+       /*
+        * The code described by the comment below has been removed
+

Added: 
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/29_cobalt_tulip2.dpatch
==============================================================================
--- (empty file)
+++ 
dists/trunk/arch/mips/linux-patch-2.6.15-mips-2.6.15/debian/patches/29_cobalt_tulip2.dpatch
 Sun Jan 29 23:16:49 2006
@@ -0,0 +1,108 @@
+#! /bin/sh -e
+## 29_cobalt_tulip2.dpatch by Peter Horton
+
+## DP: TULIP_MWI fix for Cobalt
+
+# When you build with this new patch you need to enable TULIP_MWI *and*
+# TULIP_MWI_DC21143 for the patch to take effect (if the patch is working
+# you should get a line that says "eth?: CSR0 01a04800" in /var/log/debug
+# after booting).
+
+# P.
+
+
+if [ $# -lt 1 ]; then
+    echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+    exit 1
+fi
+
+[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts
+patch_opts="${patch_opts:--f --no-backup-if-mismatch} ${2:+-d $2}"
+
+case "$1" in
+    -patch) patch -p1 ${patch_opts} < $0;;
+    -unpatch) patch -R -p1 ${patch_opts} < $0;;
+    *)
+        echo "`basename $0`: script expects -patch|-unpatch as argument" >&2
+        exit 1;;
+esac
+
+exit 0
+
+
+Index: linux.git/drivers/net/tulip/tulip_core.c
+===================================================================
+--- linux.git.orig/drivers/net/tulip/tulip_core.c      2006-01-29 
21:43:40.000000000 +0000
++++ linux.git/drivers/net/tulip/tulip_core.c   2006-01-29 21:56:50.000000000 
+0000
+@@ -294,6 +294,8 @@
+       if (tp->mii_cnt  ||  (tp->mtable  &&  tp->mtable->has_mii))
+               iowrite32(0x00040000, ioaddr + CSR6);
+ 
++      printk(KERN_DEBUG "%s: CSR0 %08x\n", dev->name, tp->csr0);
++
+       /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
+       iowrite32(0x00000001, ioaddr + CSR0);
+       udelay(100);
+@@ -1155,8 +1157,10 @@
+       /* if we have any cache line size at all, we can do MRM */
+       csr0 |= MRM;
+ 
++#ifndef CONFIG_TULIP_MWI_DC21143
+       /* ...and barring hardware bugs, MWI */
+       if (!(tp->chip_id == DC21143 && tp->revision == 65))
++#endif
+               csr0 |= MWI;
+ 
+       /* set or disable MWI in the standard PCI command bit.
+@@ -1182,7 +1186,7 @@
+        */
+       switch (cache) {
+       case 8:
+-              csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
++              csr0 |= MRL | (1 << CALShift) | (8 << BurstLenShift);
+               break;
+       case 16:
+               csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
+Index: linux.git/drivers/net/tulip/tulip.h
+===================================================================
+--- linux.git.orig/drivers/net/tulip/tulip.h   2006-01-29 21:43:40.000000000 
+0000
++++ linux.git/drivers/net/tulip/tulip.h        2006-01-29 21:52:01.000000000 
+0000
+@@ -262,7 +262,15 @@
+ #define RX_RING_SIZE  128 
+ #define MEDIA_MASK     31
+ 
+-#define PKT_BUF_SZ            1536    /* Size of each temporary Rx buffer. */
++/* MWI can fail on 21143 rev 65 if the receive buffer ends
++   on a cache line boundary. Ensure it doesn't ...
++*/
++
++#ifdef CONFIG_TULIP_MWI_DC21143
++#define PKT_BUF_SZ            (1536 + 4)      /* Size of each temporary Rx 
buffer. */
++#else
++#define PKT_BUF_SZ            1536            /* Size of each temporary Rx 
buffer. */
++#endif
+ 
+ #define TULIP_MIN_CACHE_LINE  8       /* in units of 32-bit words */
+ 
+Index: linux.git/drivers/net/tulip/Kconfig
+===================================================================
+--- linux.git.orig/drivers/net/tulip/Kconfig   2006-01-29 21:48:09.000000000 
+0000
++++ linux.git/drivers/net/tulip/Kconfig        2006-01-29 21:50:28.000000000 
+0000
+@@ -57,6 +57,16 @@
+ 
+         If unsure, say N.
+ 
++config TULIP_MWI_DC21143
++      bool "Enable MWI workaround on dc21143 controllers"
++      depends on TULIP_MWI
++      help
++        This enables a workaround for MWI ("New bus configuration") on DC21143
++        controllers.  Normally MWI is disabled on these chips because of
++        hardware errata.
++
++        If unsure, say N.
++
+ config TULIP_MMIO
+       bool "Use PCI shared mem for NIC registers"
+       depends on TULIP
+

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