Matthew Dillon wrote:
:
:Thomas E. Spanjaard wrote:
:>>> Is not the large pages necessary for 64 GB memory support ?
:>> no. and PAE is stupid, so we won't do that. it's really stupid.
:> Actually, we will do that. Perhaps not on x86-32, but it sure is a
:> requirement for 64bit long mode on x86-64...
:what is? PAE is not, just the 4-level page table.
Nothing wrong with the 4-level page table. It's designed so you
can assign address spaces their own independant page table directories.
So, for example, the kernel would no longer need to stuff all the
kernel's PTEs into each user page table in order to keep the kernel
mapped.
yah, and you simply need it to address more than 4GB.
Besides, pretty much all the levels except the last are cached.
but they will be flushed on a task switch, right? We should check out that
GLOBAL PTE flag which prevents TLB entries to be flushed.
cheers
simon
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