Hi Matt, On Wed, Jun 27, 2012 at 4:41 AM, Matt Emmerton <m...@gsicomp.on.ca> wrote:
> Mihai,**** > > ** ** > > This is great stuff.**** > > ** ** > > For the CPU topology option, are cbits/lbits values considered a mask (eg, > reserve N bits for core ID or thread ID), or are they the log2 of the > threads/core or cores/package that you want to simulate? If it's the > latter, then I envision problems attempting to simulate systems that don't > follow strict power-of-2 scaling (such as the AMD Phenom X6 that I'm > writing this on, with 6 cores/package.) > Those are the number of bits within the APICID, from where you can get the core ID and the thread ID. For each available CPU, these IDs are compared to BSD ID (the cpu0 which does the init). Based on this, the cpu topology is discovered. Because is a virtual environment and there is no APICID (the APICID = CPUID basicly), yes you cannot simulate an AMD Phenom X6 (the cpuid's are consecutive). But I'm curious if the real code works on your Phenom X6. Could you compile my repo and then issue a sysctl kern.cpu_topology? Thank you, Mihai
