Mihai, Dillon tried this out on monster, the 48-core Opteron and it seems like it got a little confused, output in the link below:
http://apollo.backplane.com/DFlyMisc/smt.txt Sam On Sun, Jun 3, 2012 at 5:00 AM, Mihai Carabas <mihai.cara...@gmail.com>wrote: > Hello, > > This week, I managed to *dynamicly detect *the CPU topology of a > platform. There are 2 components: platform depedent code which determines > the mask_size within APICID for logical and core ids. For now, is available > only for 64bit, intel and amd (I will make code available for 32bit soon). > The code was written here [1], from line 1107. > > Another component, is the platform independent. I used the > logical_CPU_bits and core_bits to determine the number of entities per > level and build a topology tree (I tried to make all as general as > possible). For this code I added a new file [2]. The init function is > registered through SYSINIT to run before the initialization of the > USCHED. All the topology information is available through sysctl. > > Here are outputs for 3 different topologies. Unfortunately, I don't have > an AMD platform to test on. All tests are done on INTEL platforms. > > *1) two physical CPUs (emulated through VMWARE - yes vmware gives this > posibility)* > > hw.cpu_topology.tree: > \-PACKAGE MEMBERS: cpu0 cpu1 > |-CHIP ID 0: cpu0 > \-CHIP ID 1: cpu1 > hw.cpu_topology.members: cpu0 cpu1 > > hw.cpu_topology.cpu0.physical_id: 0 > hw.cpu_topology.cpu0.physical_sibings: cpu0 > > hw.cpu_topology.cpu1.physical_id: 1 > hw.cpu_topology.cpu1.physical_sibings: cpu1 > > > *2) two cores on one physical CPU* > > hw.cpu_topology.tree: > \-PACKAGE MEMBERS: cpu0 cpu1 > \-CHIP ID 0: cpu0 cpu1 > |-CORE ID 0: cpu0 > \-CORE ID 1: cpu1 > hw.cpu_topology.members: cpu0 cpu1 > > hw.cpu_topology.cpu0.physical_id: 0 > hw.cpu_topology.cpu0.physical_sibings: cpu0 cpu1 > hw.cpu_topology.cpu0.core_id: 0 > hw.cpu_topology.cpu0.core_siblings: cpu0 > > hw.cpu_topology.cpu1.physical_id: 0 > hw.cpu_topology.cpu1.physical_sibings: cpu0 cpu1 > hw.cpu_topology.cpu1.core_id: 1 > hw.cpu_topology.cpu1.core_siblings: cpu1 > > > *3) two cores on one physical CPU and two threads on each core.* > > hw.cpu_topology.tree: > \-PACKAGE MEMBERS: cpu0 cpu1 cpu2 cpu3 > \-CHIP ID 0: cpu0 cpu1 cpu2 cpu3 > |-CORE ID 0: cpu0 cpu2 > | |-THREAD ID 0: cpu0 > | \-THREAD ID 1: cpu2 > \-CORE ID 1: cpu1 cpu3 > |-THREAD ID 0: cpu1 > \-THREAD ID 1: cpu3 > hw.cpu_topology.members: cpu0 cpu1 cpu2 cpu3 > > hw.cpu_topology.cpu0.physical_id: 0 > hw.cpu_topology.cpu0.physical_sibings: cpu0 cpu1 cpu2 cpu3 > hw.cpu_topology.cpu0.core_id: 0 > hw.cpu_topology.cpu0.core_siblings: cpu0 cpu2 > > hw.cpu_topology.cpu1.physical_id: 0 > hw.cpu_topology.cpu1.physical_sibings: cpu0 cpu1 cpu2 cpu3 > hw.cpu_topology.cpu1.core_id: 1 > hw.cpu_topology.cpu1.core_siblings: cpu1 cpu3 > > hw.cpu_topology.cpu2.physical_id: 0 > hw.cpu_topology.cpu2.physical_sibings: cpu0 cpu1 cpu2 cpu3 > hw.cpu_topology.cpu2.core_id: 0 > hw.cpu_topology.cpu2.core_siblings: cpu0 cpu2 > > hw.cpu_topology.cpu3.physical_id: 0 > hw.cpu_topology.cpu3.physical_sibings: cpu0 cpu1 cpu2 cpu3 > hw.cpu_topology.cpu3.core_id: 1 > hw.cpu_topology.cpu3.core_siblings: cpu1 cpu3 > > Now, every CPU, have in its own structure, the knowledge of the whole > topology. The next step is to develop some meaningful tests and begin > playing with scheduling decisions. Scheduling will take into account the > load of the target's siblings cpu, too. > > For those who want to test this, they have to clone the repo [3]. May be > next week, if you want, I will make a full patch with my code till now. > > Any feedback is welcome! > > Thanks, > Mihai Carabas > > [1] > https://github.com/mihaicarabas/dragonfly/blob/master/sys/platform/pc64/x86_64/mp_machdep.c > [2] > https://github.com/mihaicarabas/dragonfly/blob/master/sys/kern/cpu_topology.c > [3] https://github.com/mihaicarabas/dragonfly >
