The CPU always reads at its word size (4 bytes on a 32-bit processor), so when you do an unaligned address access — on a processor that supports it — the processor is going to read multiple words. The CPU will read each word of memory that your requested address straddles. This causes multiple processor read to access the requested data.
Hardware deals with word size alignment. Other alignment like page size alignment is a software feature. On X86: Any virtual address provided to cpu is split into page aligned virtual address and an offset.CPU uses page aligned virtual address to check TLB to get page aligned physical address. Now physical address = Page aligned physical address + offset If page size is bigger then less no of TLB entries are required for the processor. Each page needs one TLB entry. Regards Manoj Nayak
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