Thanks for answering. On Jan 29, 2008 1:16 AM, Rene Herman <[EMAIL PROTECTED]> wrote:
> On 28-01-08 17:12, Peter Teoh wrote: > > > In Documentation/DMA-mapping.txt: > > > Some related question (apologies for the basic questions, as I am not much of h/w, but attempting to analyse the s/w implementation - just a short conceptual one-liner or some keywords will do): a. Access to main memory by devices vs CPU is sequentially accessed - possible or right (ie, multiple concurrent signals on the system bus happening at the same time is not allowed?) So this means that whenever hardware accessing/updating the memory, there is no worry on the CPU/linux kernel side about concurrently accessing a block of memory that is being updated by h/w devices at the same time. Correct? b. And in dual core/quadcore, there is still only one system bus is shared among the 4 CPU - for Intel north-south bridge architecture, right? But in AMD hypertransport the different parts of the memory can be accessed at the same time by different CPU? (NUMA?) c. Supposed there are N h/w devices wanting to access the main mem via DMA, so all of them have to go through a DMA controller for memory mapping. So it is impt on the software or BIOs side to ensure that the physical address allocated to these devices does not collide among themselves, correct? Is this done in kernel and/or BIOs? Thanks a lot.
