I have a new comprehension about the question according to your clue

The "SP" register(R13) is a banked register, there is a corresponding physical 
register for each processor mode(abort fiq irq svc und ...), so in this case, 
when a normal interrupt exception occurs, the processor(arm core) auto enter 
irq mode, then the "SP"(R14) is "R14_irq", so the SP isn't the pointer of 
kernel stack.

I don't know this comprehension is correct or no?

According to this comprehension, there is also an uncertainty.
where is the "R14_irq" register initialized?

-----邮件原件-----
发件人: Pei Lin [mailto:[email protected]] 
发送时间: 2009年7月31日 10:29
收件人: 付新荣
抄送: [email protected]; Kernelnewbies
主题: Re: 答复: 答复: Ecartis command results: appsub kernelnewbies 
[email protected] 4A71650B:26CF.1:xrearyarjovrf

see the comment "
 * SP points to a minimal amount of processor-private memory, the address
 * of which is copied into r0 for the mode specific abort handler.
"
i think here it build a stack for exception handling.

BRs
Lin


2009/7/31 付新荣 <[email protected]>:
> Thank you for your reply!
>
> I make a mistake before.
> The "sp" should decrement before storing rather than after.
> So it's should "stmdb sp, {r0, lr}"
> The "stmdb" is equivalent to "stmfd".
> So i am in accordance with u in this matter!
>
> But,
> How to explain the "stmia       sp, {r0, lr}" of the micros "vector_stub" 
> defined in file "arch/arm/kernel/entry-armv.S".
>
> Are there different comprehension in this problem?
>
> Thax!
>
> -----邮件原件-----
> 发件人: [email protected] 
> [mailto:[email protected]] 代表 [email protected]
> 发送时间: 2009年7月30日 22:01
> 收件人: Kernelnewbies
> 主题: Re: 答复: Ecartis command results: appsub kernelnewbies 
> [email protected] 4A71650B:26CF.1:xrearyarjovrf
>
> On Thu, 30 Jul 2009 18:07:18 +0800, 付新荣 <[email protected]>
> wrote:
>> hi,everybody.
>> I don't know why use the "stmia       sp, {r0, lr}" instruction rather than
>> "stmda sp, {r0, lr}" in the macros "vector_stub" defined in file
>> "arch/arm/kernel/entry-armv.S".
>>
>> becaue the "sp" register is point to the kernel stack top.
>> The "sp" register is initialized with "init_thread_union +
> THREAD_START_SP"
>>
>>
>> Kernel stack:
>> =======================================================================
>> Lower address                                                                
>>          higher address
>> | init_thread_union|                          <-------stack content--------|
>>                                                               sp
>> |<----------------------------8K bytes--------------------------->|
>> =======================================================================
>>
>> According to the Kernel stack mechanism,I think that it should be
> "stmda
>> sp, {r0, lr}" and the SP should decrement.
>>
>> -----邮件原件-----
>> 发件人: Ecartis [mailto:[email protected]]
>> 发送时间: 2009年7月30日 17:39
>> 收件人: 付新荣
>> 主题: Ecartis command results: appsub kernelnewbies
>> [email protected] 4A71650B:26CF.1:xrearyarjovrf
>>
>>
>> List context changed to 'kernelnewbies' by following command.
>>>> appsub kernelnewbies [email protected]
>>>> 4A71650B:26CF.1:xrearyarjovrf
>> Subscribed.
>>
>> ---
>> Ecartis v1.0.0 - job execution complete.
>>
>>
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>
> Hi,
>
> I don't know the intrinsics of the kernel stack, but the stack described is
> indeed a full descending stack.
> If pushing on the stack, it's more common to use the stmfd instruction
> though. (IOW store on a full descending stack)
> I guess it depends whether the excerpt of code is aiming to push or to pop
> the stack.
> It should be pushing, since the sp is the destination for the storing of
> all registers + link register...
>
> B rgds
> Kris
>
>
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