Without the CPSR register, gdb is unable to correctly step over a
conditional branch.  This is because it cannot see the condition code
bits, and thus cannot determine which side of the branch to place the
breakpoint.

This patch fixes the register layout of the registers passed to the host
gdb so that CPSR is properly interpreted.

Signed-off-by: Kevin Hilman <[EMAIL PROTECTED]>

Index: linux-2.6.18/include/asm-arm/kgdb.h
===================================================================
--- linux-2.6.18.orig/include/asm-arm/kgdb.h
+++ linux-2.6.18/include/asm-arm/kgdb.h
@@ -52,15 +52,23 @@ extern int kgdb_fault_expected;
 #endif /* !__ASSEMBLY__ */
 
 /*
- * From Amit S. Kale:
+ * From Kevin Hilman:
  *
- * In the register packet, words 0-15 are R0 to R10, FP, IP, SP, LR,
PC. But
- * Register 16 isn't cpsr. GDB passes CPSR in word 25. There are 9
words in
- * between which are unused. Passing only 26 words to gdb is
sufficient.
- * GDB can figure out that floating point registers are not passed.
- * GDB_MAX_REGS should be 26.
+ * gdb is expecting the following registers layout.
+ *
+ * r0-r15: 1 long word each
+ * f0-f7:  unused, 3 long words each !!
+ * fps:    unused, 1 long word
+ * cpsr:   1 long word
+ *
+ * Even though f0-f7 and fps are not used, they need to be
+ * present in the registers sent for correct processing in
+ * the host-side gdb
  */
-#define        GDB_MAX_REGS            (26)
+#define _GP_REGS 16
+#define _FP_REGS 8
+#define _EXTRA_REGS 2
+#define        GDB_MAX_REGS            (_GP_REGS + (_FP_REGS * 3) + 
_EXTRA_REGS)
 
 #define        KGDB_MAX_NO_CPUS        1
 #define        BUFMAX                  400


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