Sergei Shtylyov wrote: > Update arch/ppc KGDB implementation: > > - merge the begginning of trap-to-signal table containing the more or less > standard traps for all CPU families; > > - make the instruction access trap generate SIGSEGV just like its data access > counterpart; > > - add some traps specific to Freescale E200/E500, Book E, 40x, 6xx/74xx, and > 8xx CPU families; > > - remove PPC64 data/instruction segment trap codes as they never reach the > high level code anyway; > > - remove table entries for the reserved trap since they should be translated > to SIGHUP anyway; > > - make the code dealing with the SPE registers also compile for Freescale E200 > CPUs and fix it to correctly skip over if SPE support is not enabled; > > - fix sleeping_thread_to_gdb_regs() to use the specified (and not the current) > process' context to retrieve the SPE accumulator and SPEFSCR; > > - skip over the $r3-$r13 and FP registers do it without duplicate zeroing; > > - fix coding style (moved/renamed some variables, removed useless parens, > etc.); > > - fix typos in the comments... > > Signed-off-by: Sergey Shtylyov <[EMAIL PROTECTED]> > > Committed to powerpc-lite.patch in linux2_6_21_uprev branch.
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