George G. Davis wrote: > Hi, > > On Mon, Apr 12, 2010 at 06:32:47PM +0100, Russell King - ARM Linux wrote: > > On Mon, Apr 12, 2010 at 06:23:58PM +0100, Will Deacon wrote: > > > This patch changes the definition of cpu_relax() to smp_mb() for ARMv6 > > > cores, > > > forcing the write buffer to drain while inside a polling loop on an SMP > > > system. > > > If the Kernel is not compiled for SMP support, this will expand to a > > > barrier() > > > as before. > > If I've followed these threads [1][2] correctly, this ARM11 MPCore issue > was discovered while running the "KGDB: internal test suite" (KGDB_TESTS) > and that problem is resolved via "kgdb: use atomic_inc and atomic_dec > instead of atomic_set" [3]. If so, isn't the original ARM11 MPCore KGDB > cpu_relax() issue just a red herring? Shouldn't any polling loops > which depend on specific (hardware) write/read order implement appropriate > barriers rather than rely on cpu_relax() to guarantee order?
Note that the need to force the write buffer to drain is _not_ an ordering issue. It's a buffer draining issue. :-) I'm not sure if Linux smp_wmb() guarantees to ensure prior writes will be visible to other CPUs in a short time, or if it only guarantees write order. -- Jamie ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev _______________________________________________ Kgdb-bugreport mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/kgdb-bugreport
