On Sat, Apr 06, 2013 at 08:07:40PM +0300, Vesa Solonen wrote: > Every net has a general design rule that defines a minimum clearance > etc. Potential classes would be implemented by giving potential range > numbers to the net, and these rules must also be definable towards a > group of nets. These potential numbers would be used for clearances > between the nets, because not all of them are equal like in the current > DRC system.
You could do without the 'potential' classes, just allow for netclass to interact between them. Having 'macro classes' would be cute but not necessary. In a typical design of ours we would have: mains power (usually 230VAC), actuators power (24V AC or DC) and board power (often divided in logic and analog). Clearance between mains and mains would be different than from mains and logic. In a similar way balanced lines would have a clearance between the pair, one with ground and one with... everything else; it also depends if the line is actually a transmission line (like a microstrip) or 'only' a differential pair (which is a little easier). The difficult thing would be designing an interface to manage these relationship, there could be many of them. > There must also be a way for defining these in the schematic UI, because > with complex designs PCB phase is too complicated to track everything > properly. The way for splitting a net to say "contol" and "power" sides > must also be available. Uhm a net itself shouldn't be split. Please elaborate on that. Doing mixed signal and power on the same board I usually have at least two grounds (usually 3, on one issue 4), all 'teorically' at 0V (yeah, sure:D) I implement them as *different* net with 'virtual' modules doing the potential bonding (I have a whole lib of them, of various size and shapes). You can see the technique even in HP service manual (they use a funny star symbol to indicate star bonds). Well, they also put in the schematic guard tracks but luckily not everyone has to design 6 digits DMM... > Control and power split is at the T- and X-junctions towards the control > side. Clearances: small between [PGND, LS, LG] and between [HS, HG, > OUT], large between [HV, OUT, everything else]... I use star point as your T- and X- junctions. This also document in the schematic where the transition is (which is maybe more important than the layout). Simple example: the output rails (hot from the MOS or whatever), labeled, say, VOUT, has to be branched for the feedback divider. Star point (which give me a new net) and I can name it appropriately if I want (VOUT:FB, maybe). Probably I would label the divider output, instead, since *that* is high impedance and more susceptible. However branching with a star allow me to change net class and use (for example) a smaller track (clearance in this case would be the same). Sadly high voltage (from about 60VDC up) clearances are not so easy to define:P there is clearance and there is creepage which are extremely different thing (governed by solder mask and board shape). And it's not unusual to cut a slot in the board to gain creepage distance (but not clearance!). IEC60950 has all the scary details, and I have never seen a tool implementing all of the needed features (I don't think you could actually do every check automatically). Anyway I feel that assigning net classes from eeschema would be very useful. That could be done after the work in progress (according to the bug db) on 'persistent' net names. > Implementing this DRC and automation feature would allow painless usage > of KiCad for power layouts. Currently it needs switching off the DRC and > making any adjustments afterwards is very error prone. Failing the > UL-test because of the 100um layout error can be costly too. Also making > the tool a bit smarter would allow separating the layout person and > schematic design person. Maybe not completely, but most of the > information would be automatically conveyed within the design files. You fail UL test; TÜV or similar tests (the european equivalent of UL) are even more stringent! True story: for a gas valve control we had to put THREE safety rated relays in series each with the coil driven both from power and to the ground. And TWO microcontroller to drive them: one drives 2 p-channels and 1 n-channel, the other one the other 3 FETs; *both* of them reading *different* feedback contacts from each relay. And that's for a gas burner to cook pasta :D project has been scrapped because too expensive :((( -- Lorenzo Marcantonio Logos Srl _______________________________________________ Mailing list: https://launchpad.net/~kicad-developers Post to : [email protected] Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
