On Fri, Apr 26, 2013 at 08:48:52PM -0500, Dick Hollenbeck wrote: > It will definitely be a bottleneck. Maybe we should measure how bad soon, > otherwise this > is a suggestion which serves as a roadblock to progress, and the roadblock > itself it not > currently a solution.
I don't trust much python speed... however some heavy caching could help, if needed. OTOH if you have ever seen the speed of the CAM350 'streams' checker:P I have to admit it's designed to be a pre-production final check but 40 minutes for a small 4 layers board (about 500 nets) are a little too much > The idea is innovative, and if it is not like watching snails race, it may > have some merit. I fear that could be unapproachable for the 'common' user. What about surveying what other cads are using and pick the more useful/less esoteric ones? For example, different clearances on different parts of the board would a) need some kind of partitioning tool and b) only of really specialistic use (AFAIK only for multideposition or hybrid boards...) Instead of booleans we could use some kind of truth table to check the needed conditions (like for syslog-ng filtering or apache httpd ACLs), that would be a lot more usable. Some thinking about use cases is needed here. The result is actually equivalent to a sum-of-product normal form, so I think we would not lose flexibility. Also this kind of 'programmable' clearance (be it done in python or in tabular form) would implement interclass clearance. Before of this I think that some better way to assign netclasses is needed (preferably from eeschema, thru the netlist, maybe). Having to crosscheck between pcbnew and labels on eeschema is way too error prone. -- Lorenzo Marcantonio Logos Srl _______________________________________________ Mailing list: https://launchpad.net/~kicad-developers Post to : [email protected] Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
