I added back annotation to Eeschema directly from Cvpcb when they are both
running under
Kicad.exe.
I could have done it row by row. Instead I did it as a group batch when you
"save" under
cvpcb, on the idea that if you were to abort cvpcb without saving, you would
not want to
affect your schematic.
For the TODO list, I think we have a problem with the hierarchical format.
Here is a
takeout from a nested schematic, used six times in the hierarchy:
$Comp
L R R1
U 1 1 520135B0
P 5400 3350
AR Path="/5201406D/520135B0" Ref="R1" Part="1"
AR Path="/52014588/520135B0" Ref="R2" Part="1"
AR Path="/52014893/520135B0" Ref="R3" Part="1"
AR Path="/520134DE/520135B0" Ref="R4" Part="1"
AR Path="/52015233/520135B0" Ref="R5" Part="1"
AR Path="/520155E6/520135B0" Ref="R6" Part="1"
F 0 "R2" V 5500 3450 60 0000 L CNN
F 1 "R" V 5300 3450 60 0000 L CNN
F 2 "Discret:R6" H 5520 3450 60 0001 C CNN
F 3 "" H 5400 3350 60 0001 C CNN
1 5400 3350
0 -1 -1 0
$EndComp
$Comp
If CVPCB sets only R3, and not the others, then the back annotation does not
stick. This
is not new that I can tell, I believe it failed this way when doing back
annotation with
the *.cmp file also. The code between the two means is similar.
I used an s-expression on the KIWAY express, and parsed it with the DOM
s-expression
parser in about 5 lines of code.
See SCH_EDIT_FRAME::backAnnotateFootprints()
Jean-Pierre, what do you think?
Dick
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