On 19.03.2016 19:11, Chris Pavlina wrote: > Hey, just wondering about something. PNS has had slightly different rounding > behavior than DRC since the beginning - when I use PNS heavily on a board, I > usually have to decrease my clearance very slightly (say from 0.2mm to > 0.199mm) > to make DRC pass. Is this a known issue among the devs working on GAL/PNS, and > is there any plan to do something about it? I suppose it's probably quite > difficult to make PNS perfectly emulate the behavior DRC uses - maybe we could > do something like applying a very small error margin to the clearance in PNS > so > it doesn't route things *exactly* to the clearance? >
Hi Chris, We know about it, the DRC calculates clearances in a completely different way than P&S, so rounding errors are to be expected. Your idea with applying a small margin looks OK to me. BTW - could you send me the PCB design which shows most of P&S-caused DRC errors? Cheers, Tom _______________________________________________ Mailing list: https://launchpad.net/~kicad-developers Post to : [email protected] Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
