On Dec 19, 2017, at 1:28 PM, Jon Evans <[email protected]> wrote: > 2) Design needs multiple copies of a similar bus with distinct net names > > Say you are designing a big data collection device. It has a large FPGA and > 8 channels of ADC. Each ADC needs its own set of signals going straight back > to the FPGA (i.e. no shared signals between the ADC) > You could define buses going to each ADC like this: > > "CH0{D[15..0] CLK_P CLK_N}" > "CH1{D[15..0] CLK_P CLK_N}" > and so on. > > This would leave you with nets for each ADC like "CH0.D15", "CH0.CLK_P", etc > > Now you could *optionally* also define an alias for the signals each ADC > needs: > > "ADC" => "D[15..0] CLK_P CLK_N" > > Then, you could name your ports/pins/buses like: > > "CH0{ADC}" > "CH1{ADC}" > and so on. > > Benefit 1: Even if you don't use aliases, putting a name in front of the bus > group means that each channel will get its nets automatically prefixed with > "CH0" etc. > Benefit 2: If you use aliases, your port/pin/label names get much shorter, > the same as in the first example.
Oh, good god, I would have given my eyeteeth (which I no longer have) for this exact feature on my current design. It supports up to four (but normally just two) high-speed (40 MHz sample rate) octal ADCs, each with all LVDS, with bit clock, frame clock and DDR serial data lines, all going to a big FPGA. The ADCs are on one page, the FPGA is on another, and it’s a mess of lines. A nice way to roll all of that up into your buses would have been very handy. _______________________________________________ Mailing list: https://launchpad.net/~kicad-developers Post to : [email protected] Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
