Looking through our current set of board setup properties, only solder_mask_min_width would join edge_clearance in a design_rules section.
Most of the other properties are either most-recently-used values (zone_clearance, via_size, etc.) or true DRC values (uvias_allowed, trace_min, etc.). The outlier is max_error, which is mostly a performance vs beauty trade-off, but does affect the generated board. So, 1) leave solder_mask_min_width and edge_clearance in setup for now 2) create a design_rules section for solder_mask_min_width and edge_clearance 3) leave edge_clearance in the project file for now I think I’d vote for (1) simply because I don’t know how (2) will play with Jon’s stuff. But the only one I don’t like is (3). Cheers, Jeff. > On 4 Jul 2019, at 15:42, Seth Hillbrand <[email protected]> wrote: > > On 2019-07-04 09:24, Jeff Young wrote: >>> Since this is DRC, can we keep it in its current place until the DRC >>> manager goes in >> Well, there’s DRC and there’s DR. The other options really control >> only what is *checked*, whereas this one controls stuff *on* the >> board. Granted a lot of Jon’s rules will also fit into the DR camp, >> but I feel a little more reticent to move this one out. >> Thoughts? >> Jeff. > > That's a valid point. Ideally, I'd like to see this in a "DesignRules" > section. Different manufacturers will have different requirements here, so > the DRC/DFM import would need to modify this value. The check also needs to > allow separate values for internal vs. external layers. > > If we want to separate the generation from the checking, we might want to put > this setting in the zone parameters. In which case, we might use a global > default setting that is used for new zones. > > -Seth
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