--- In [email protected], "Frank Bennett" <[EMAIL PROTECTED]> wrote: > > > > Note: I just found a bug: zero length pins are missing from > > the power symbols: CAPSYM/VCC_BAR, GND_SIGNAL. Workaround: > > edit symbols & add pin. > > > This has been fixed and checked into svn. The netlist output > from EEschema now has VCC, GND nets.
Which is better than no power nets but this examples/eyespy (TI app note for an ATX power supply) and other designs would require edits to the symbol to provide multiple power nets such as +3v3, +5V, +5VSB, AGND, etc, information not included in the OrCad EDIF out file. > And a new revision 20071101 zipped tar file has been released for folks lacking svn access.
