Hi all,
I found that there is a strange behavior when I generate the netlist by
eeschema, for the next processing in pcbnew.
I made a pcb with a lot of areas connected to respective nets, but when
I re-generate the netlist, some netnames ( or all ) changes and I have
to reassign the netlist name for every areas. It's very annoying...

(and in the new SVN version there is alwys the problem of decimal
separator for windows ... ).

Bye, Leonardo.


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