--- In [email protected], Dave - WB6DHW <brain...@...> wrote: > > But ONE component is not "wired up" when I select "Show general ratsnest". > > As far as pcbnew the component is NOT connected. > > BUT IT IS! At least as the netlist is concerned. How can this happen? > Does your footprint for Q1 use pins 1, 2, and 3 or pins D, G, and S? > With your netlist, pcbnew will be expecting pins D, G, and S. If it > finds 1, 2, and 3, they are not in the netlist.
Thanks Dave (and David) for the quick response. This was it: problem solved. Apparently this is not avoided by cvpcd, which could be done I guess. Thanks again! Sietse
