I am seeing this very strange issue when using zones (at least it seems strange to me).I have a 4-layer board with almost all surface mount. L1 is almost entirely dedicated as my "VDD layer" by creating a zone connected to my VDD net on that layer. L2 is the same thing with my VSS (Ground) layer.
When I want to connect a pad or trace to VDD or VSS, I simply place a via in
the trace. According to the 3D view of the board, the hole plating is
connected to the VDD or VSS layer as I would expect.
