Kicad has nice text file formats and netlists can its netlist go to verilog?
Can it's netlists go to geda's netlist? or the schematics be converted to draw the sch in kicad and make the verilog code from geda's netlister? http://www.geda.seul.org/wiki/geda:verilog_netlister_readme Yes someone who is fluent in verilog could proably do a jiant processor in it faster better and shorter than if done in schematic capture. But lets say if I want some simple parrellel additon subtraction and ing or ing and shifting.... maby schematic capture is easier with kicads herarchal sheets.... Well I would like to hear what people have to say.
