Hi Josh; I'm not sure of everything you mention, I wish you the best with your research and use of FPGAs.
I have experience with the Xilinx tools. The VHDL code I've written by hand is largely generic and the Xilinx tools appear happy with straight VHDL, without concern of where the VHDL code came from. Maybe some day I'll get to Verilog. Jonathan --- In kicad-users@yahoogroups.com, "josh_eeg" <josh...@...> wrote: > > I read quite a lot on tkgate & it seems realy cool for testing but xilinx > still seems like the only one that makes something that will compile at least > to my understanding the documentation says like verilog so it is close but > not compiling. xilinx stuff I may use because it is there and learning > another language won't get me the device I want to make any faster & the > maple arm3 won't do multi channel blind source seperation on my adc's inputs > in real time. > > --- In kicad-users@yahoogroups.com, "jmhill.hartford" <jmhill.hartford@> > wrote: > > > > Hi Folks; > > > > Just found this thread. I have an interest in making more use KiCad. I > > already use KiCad for schematics and PC board layout. I have two items on > > my wishlist. > > > > o Be able to convert a KiCad schematic to a VHDL structural type > > description of a circuit. This would be helpful for an undergraduate logic > > circuits course. > > > > I see that the .lib file format includes pin direction information and that > > the netlist describes connections between pins. Perhaps a utility can be > > written to produce such a VHDL structural description. What do you think? > > I can certainly give it a try. > > > > o Be able to convert a part of a schematic to a VHDL structural > > description. I have students using KiCad to draw schematics which make > > some use of CPLDs. > > > > In any case, some discussion would be appreciated. > > > > Thanks; > > Jonathan > > > > --- In kicad-users@yahoogroups.com, "Frank Bennett" <bennett78@> wrote: > > > > > > --- In kicad-users@yahoogroups.com, Lothar Behrens <lothar.behrens@> > > > wrote: > > > > > > > > Hi, > > > > > > > > I think, this is not the main intention of KICAD, but as of the > > > > availability of spice samples, is there also a way to use KICAD for > > > > FPGA design? > > > > > > > > Say, I would use a sub sheet to enter a group of logic to be placed > > > > into a FPGA (reduced set of symbols only) and a tool that > > > > translates the usual netlist into a VHDL file. > > > > > > A schematic of Xilinx primitives..dump VHDL (ADA like) and become > > > twice as productive using Verilog (C like). Some good OpenSource > > > Simulators are: cVer and Icarus with gtkWaves. The FPGA tools accept > > > Verilog as well as VHDL. > > > > > > Check out TKGate (http://www.tkgate.org/), the hierarchical > > > schematic is actually a verilog netlist with the graphical > > > information included as comments. It also includes a simulator. > > > > > > EEschema actually does a better job than TKGate with the relation > > > to pins on a schematic page to the ports on the corresponding > > > sheet(module). Adding one should automatically produce the other. > > > (an unfullfilled enhancement request to the TKGate author) With > > > TKGate one has to enter each redundantly. There is a tool called > > > SpeedChart which is cool for this but cost $s... or Summit Design, > > > which I didn't like as well... > > > > > > EEschema also seems to need some work handling: > > > bundles (i.e. {cas, ras, cs[1:0], we} ) verses pure > > > buses - a[15..0] (I would have prefered a[15:0]) > > > both should be allowed in bus rippers and across port > > > boundaries to realize continuous assignments like: > > > assign ctrl[2:0] = {cas, ras, we}; > > > > > > TKGate could also include a "comment" on a schematic page > > > that would be included inline as RTL code, then alternately > > > an AND2 primitive could include something like: > > > "code: assign y= a & b;" > > > > > > One of my ole favorites (before Verilog-A) for a resistor or > > > module NetAlias(a,a); > > > inout a; > > > endmodule > > > > > > happy HDLing, > > > Frank Bennett > > > > > > > A possible attempt may be supporting the 74XX series of IC's or some > > > > to most of them to be known in a translation tool based > > > > on the netlist. A barrier to the outer circuit (the pins of a FPGA) > > > > would be all these wires, contacting unsupported components, > > > > eg, they could not translated to be in a FPGA design, but in the outer > > > > area. > > > > > > > > Using the sub sheet would be a helper in separating FPGA related logic > > > > from the outer area. (I think I could not distinguish between > > > > signals on different sheets in a netlist, thus I don't see the pins > > > > that connects sheets) > > > > > > > > While this could be tried with the plain netlist, a netlist in XML > > > > format would be another option to enable various transformations. > > > > > > > > Is this possible? > > > > > > > > There are other tools available for this, but a first step entry with > > > > KICAD would be fine, as I work on Mac OS X and there are less > > > > EDA tools available (known by me). > > > > > > > > Thanks > > > > > > > > Lothar > > > > > > > > -- | Rapid Prototyping | XSLT Codegeneration | http://www.lollisoft.de > > > > Lothar Behrens > > > > Heinrich-Scheufelen-Platz 2 > > > > 73252 Lenningen > > > > > > > > > >
