Hi, We have the following Need for a Design & Validation Engineer Needed - Austin, TX . Please find if you are comfortable with the given job need and send me your Updated Resume along with your expected rate for this project ASAP.
Job Title: Design & Validation Engineer Position : 1 Location : Austin, TX Duration : 6 months Job Description: Exhaustive hands-on experience in Verilog / System Verilog, Shell Scripting. Experience on Altera Q-II flow, Cadence Build Gates / PKS Synthesis tool and Linux environment is highly desirable. Design experience in PCIe, HDMI, HD-SDI, Image Processing Pipeline, DDR3C, H.264, XAUI, J2K Decoder etc. Logic block is preferable Regards...!! Yunus Phone: 925-353-3776 | [email protected] -- You received this message because you are subscribed to the Google Groups "KNOW.IT" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/know_it_az?hl=en.
