Title: ASIC Verification Engineer Location: San Jose, CA 95110 Length of Assignment: 6 – 10 months
Description: Need senior level 8+ year ASIC Verification engineer to perform functional verification for complex networking chipsets. Should have solid understanding of “object oriented” verification languages. Our current verification models are written in C++ and some with SystemVerilog. Ideal candidate will have strong C++ for verification. Of course, standard Verilog is required. Any skills with networking chipsets is desired (such as: packet filtering, packet processing, etc.). -- You received this message because you are subscribed to the Google Groups "KNOW.IT" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/know_it_az?hl=en.
