Hello people,
I've found a very annoying bug, yet I don't really have time to investigate it deeply. Here is the entry in the bugtracker: https://sourceforge.net/tracker2/?func=detail&aid=2687692&group_id=143459&atid=755588 . It's about connecting logic outputs together using resistors. Instead of forming an algebric mean between the voltages, se simulator makes the voltage on logical output aproximately equal. Another think: (Jason, ) what's the situation with the new release? Zoltan ------------------------------------------------------------------------------ _______________________________________________ Ktechlab-devel mailing list Ktechlab-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/ktechlab-devel
