P Zoltan wrote: > Isn't the problem caused by the fact that the simulator has only 1kHz > step frequency? We should separate the real-world time pass speed > (simulator step at 1kHz) and the time flowing inside the circuit. This way > by "slowing" the time inside the circuit, we could simulate circuits at > any frequency.
Here are the known limits: linear update rate: 10khz, (1e4 in the code). As a function of the linear update rate, the analog signal generators are limited to 1khz. The logic update rate is about a hundred times faster (1e6). The natural limit of a logic clock is therefore 5e5. But its current limit appears to be 1e4. =\ -- New president: Here we go again... Chemistry.com: A total rip-off. Powers are not rights. ------------------------------------------------------------------------------ Come build with us! The BlackBerry® Developer Conference in SF, CA is the only developer event you need to attend this year. Jumpstart your developing skills, take BlackBerry mobile applications to market and stay ahead of the curve. Join us from November 9-12, 2009. Register now! http://p.sf.net/sfu/devconf _______________________________________________ Ktechlab-devel mailing list Ktechlab-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/ktechlab-devel
