WADE MAXFIELD wrote: > Is there any support for developing KtechLab schematic to Verilog outputs > for PSoC family (or even embedded FPGA) so that we can do visual design (for > small projects)? > > I have thick skin, so feel free to flame away. Everyone has an opinion, and > everyone’s opinion is correct, when taken in the context in which it is given.
I like the idea. I've been out of the ktechlab loop for 10+ years beacause of version miss-matches with my local machine. FPGAs are definitely on the rise, Intel has bought Altera and AMD is looking to buy Xilinx and both are likely to add reconfigurable cores to their processors and/or bring them into more mainstream products, designing efficient code for these will be an increasingly important area of development. If i remember the architecture of this program at all at this point, it would be a new document type that would be added to a project. I'm not sure how scalable that will be as a FPGA can have millions of gates. A few thousand gates, sure, but millions, that requires a higher level approach.. -- The vaccine is a LIE. #EggCrisis The Great Reset Powers are not rights. _______________________________________________ Ktechlab-devel mailing list Ktechlab-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/ktechlab-devel
