From: Zhang Xiantao <[EMAIL PROTECTED]>

Since current IA64 doesn't support dirty log, always set
whole screen as dirty. We didn't find performance loss.

In addition, this patch adds vga bios support for ia64, due
to lack of vga bios support in ia64/firmware.

Signed-off-by: Zhang Xiantao <[EMAIL PROTECTED]>
Signed-off-by: Avi Kivity <[EMAIL PROTECTED]>

diff --git a/qemu/hw/vga.c b/qemu/hw/vga.c
index 3024ebc..f82bbb5 100644
--- a/qemu/hw/vga.c
+++ b/qemu/hw/vga.c
@@ -1449,13 +1449,17 @@ static void vga_draw_graphic(VGAState *s, int 
full_update)
     /* HACK ALERT */
 #define BITMAP_SIZE ((8*1024*1024) / 4096 / 8 / sizeof(long))
     unsigned long bitmap[BITMAP_SIZE];
+#ifndef TARGET_IA64
     int r;
-
     if (kvm_allowed) {
            r = kvm_get_dirty_pages(kvm_context, s->map_addr, &bitmap);
            if (r < 0)
                    fprintf(stderr, "kvm: get_dirty_pages returned %d\n", r);
     }
+#else
+    memset(bitmap, 0xff, BITMAP_SIZE*sizeof(long));
+   //FIXME:Always flush full screen before log dirty ready!!
+#endif
 #endif
 
     full_update |= update_basic_params(s);
@@ -1868,6 +1872,138 @@ static void vga_map(PCIDevice *pci_dev, int region_num,
     }
 }
 
+#ifdef TARGET_IA64
+/* do the same job as vgabios before vgabios get ready - yeah */
+void vga_bios_init(VGAState *s)
+{
+    uint8_t palette_model[192] = {
+        0,   0,   0,   0,   0, 170,   0, 170,
+       0,   0, 170, 170, 170,   0,   0, 170,
+        0, 170, 170,  85,   0, 170, 170, 170,
+       85,  85,  85,  85,  85, 255,  85, 255,
+       85,  85, 255, 255, 255,  85,  85, 255,
+       85, 255, 255, 255,  85, 255, 255, 255,
+        0,  21,   0,   0,  21,  42,   0,  63,
+        0,   0,  63,  42,  42,  21,   0,  42,
+       21,  42,  42,  63,   0,  42,  63,  42,
+        0,  21,  21,   0,  21,  63,   0,  63,
+       21,   0,  63,  63,  42,  21,  21,  42,
+       21,  63,  42,  63,  21,  42,  63,  63,
+       21,   0,   0,  21,   0,  42,  21,  42,
+        0,  21,  42,  42,  63,   0,   0,  63,
+        0,  42,  63,  42,   0,  63,  42,  42,
+       21,   0,  21,  21,   0,  63,  21,  42,
+       21,  21,  42,  63,  63,   0,  21,  63,
+        0,  63,  63,  42,  21,  63,  42,  63,
+       21,  21,   0,  21,  21,  42,  21,  63,
+        0,  21,  63,  42,  63,  21,   0,  63,
+       21,  42,  63,  63,   0,  63,  63,  42,
+       21,  21,  21,  21,  21,  63,  21,  63,
+       21,  21,  63,  63,  63,  21,  21,  63,
+       21,  63,  63,  63,  21,  63,  63,  63
+    };
+
+    s->latch = 0;
+
+    s->sr_index = 3;
+    s->sr[0] = 3;
+    s->sr[1] = 0;
+    s->sr[2] = 3;
+    s->sr[3] = 0;
+    s->sr[4] = 2;
+    s->sr[5] = 0;
+    s->sr[6] = 0;
+    s->sr[7] = 0;
+
+    s->gr_index = 5;
+    s->gr[0] = 0;
+    s->gr[1] = 0;
+    s->gr[2] = 0;
+    s->gr[3] = 0;
+    s->gr[4] = 0;
+    s->gr[5] = 16;
+    s->gr[6] = 14;
+    s->gr[7] = 15;
+    s->gr[8] = 255;
+
+    /* changed by out 0x03c0 */
+    s->ar_index = 32;
+    s->ar[0] = 0;
+    s->ar[1] = 1;
+    s->ar[2] = 2;
+    s->ar[3] = 3;
+    s->ar[4] = 4;
+    s->ar[5] = 5;
+    s->ar[6] = 6;
+    s->ar[7] = 7;
+    s->ar[8] = 8;
+    s->ar[9] = 9;
+    s->ar[10] = 10;
+    s->ar[11] = 11;
+    s->ar[12] = 12;
+    s->ar[13] = 13;
+    s->ar[14] = 14;
+    s->ar[15] = 15;
+    s->ar[16] = 12;
+    s->ar[17] = 0;
+    s->ar[18] = 15;
+    s->ar[19] = 8;
+    s->ar[20] = 0;
+
+    s->ar_flip_flop = 1;
+
+    s->cr_index = 15;
+    s->cr[0] = 95;
+    s->cr[1] = 79;
+    s->cr[2] = 80;
+    s->cr[3] = 130;
+    s->cr[4] = 85;
+    s->cr[5] = 129;
+    s->cr[6] = 191;
+    s->cr[7] = 31;
+    s->cr[8] = 0;
+    s->cr[9] = 79;
+    s->cr[10] = 14;
+    s->cr[11] = 15;
+    s->cr[12] = 0;
+    s->cr[13] = 0;
+    s->cr[14] = 5;
+    s->cr[15] = 160;
+    s->cr[16] = 156;
+    s->cr[17] = 142;
+    s->cr[18] = 143;
+    s->cr[19] = 40;
+    s->cr[20] = 31;
+    s->cr[21] = 150;
+    s->cr[22] = 185;
+    s->cr[23] = 163;
+    s->cr[24] = 255;
+
+    s->msr = 103;
+    s->fcr = 0;
+    s->st00 = 0;
+    s->st01 = 0;
+
+    /* dac_* & palette will be initialized by os through out 0x03c8 &
+     * out 0c03c9(1:3) */
+    s->dac_state = 0;
+    s->dac_sub_index = 0;
+    s->dac_read_index = 0;
+    s->dac_write_index = 16;
+    s->dac_cache[0] = 255;
+    s->dac_cache[1] = 255;
+    s->dac_cache[2] = 255;
+
+    /* palette */
+    memcpy(s->palette, palette_model, 192);
+
+    s->bank_offset = 0;
+    s->graphic_mode = -1;
+
+    /* TODO: add vbe support if enabled */
+}
+#endif
+
 /* when used on xen/kvm environment, the vga_ram_base is not used */
 void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
                      unsigned long vga_ram_offset, int vga_ram_size)
@@ -1916,6 +2052,9 @@ void vga_common_init(VGAState *s, DisplayState *ds, 
uint8_t *vga_ram_base,
     s->update = vga_update_display;
     s->invalidate = vga_invalidate_display;
     s->screen_dump = vga_screen_dump;
+#ifdef TARGET_IA64
+    vga_bios_init(s);
+#endif
 }
 
 /* used by both ISA and PCI */

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