From: Avi Kivity <[EMAIL PROTECTED]>
Hopefully this will reduce problems on old Linux guests that assume the tsc
is synchronized.
Signed-off-by: Avi Kivity <[EMAIL PROTECTED]>
diff --git a/bios/rombios32.c b/bios/rombios32.c
index 967c119..c83aaf6 100755
--- a/bios/rombios32.c
+++ b/bios/rombios32.c
@@ -443,6 +443,12 @@ void smp_probe(void)
writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
sipi_vector = AP_BOOT_ADDR >> 12;
writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
+ asm volatile(
+ "xor %%eax, %%eax \n\t"
+ "xor %%edx, %%edx \n\t"
+ "mov $0x10, %%ecx \n\t"
+ "wrmsr"
+ : : : "eax", "ecx", "edx");
#ifndef BX_QEMU
delay_ms(10);
diff --git a/bios/rombios32start.S b/bios/rombios32start.S
index 0fe2eab..68eb17f 100644
--- a/bios/rombios32start.S
+++ b/bios/rombios32start.S
@@ -42,6 +42,10 @@ _start:
smp_ap_boot_code_start:
xor %ax, %ax
mov %ax, %ds
+ xor %eax, %eax
+ xor %edx, %edx
+ mov $0x10, %ecx
+ wrmsr
incw CPU_COUNT_ADDR
1:
hlt
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