Ingo Molnar wrote: > * Avi Kivity <[EMAIL PROTECTED]> wrote: > > >>> As SVN has shown it, we can rely on VMX state save/load to become >>> faster in the future. So we definitely shouldnt design for a >>> small-scale overhead in first-generation silicon. >>> >> In this case I think the documentation indicates their long term >> plans. However, the only real answer is to measure. >> > > yeah. Would be nice to see some hard numbers about how many cycles all > these context load/save variants take. > >
PIO latency on AMD (including a trip to qemu and back) is 5500 cycles [1]. Intel is significantly higher. [1] http://virt.kernelnewbies.org/KVM/Performance -- error compiling committee.c: too many arguments to function ------------------------------------------------------------------------- Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT & business topics through brief surveys - and earn cash http://www.techsay.com/default.php?page=join.php&p=sourceforge&CID=DEVDEV _______________________________________________ kvm-devel mailing list kvm-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/kvm-devel
