Current interrupt logic in Qemu unconditionally checks pending irqs on
PIC after checking local APIC, however, this is problematic.
On common platform, PIC is usually connected to the LINT0 of
local APIC. In this way when local APIC is disabled, this pin behaves
like INTR. But when local APIC is enabled, its behavior can be
determined by LVT_LINT0: PIC should only deliver normal irq only when
`external interrupt' delivery mode is set.
x86_64 Linux kernel uses PIT->PIC->LINT0 as NMI source when
performance counters are not available, but the logic described above
treats the NMI as normal interrupt which yields a 2x faster global timer
because an additional timer interrupt is injected on every tick. This
patch fixes this issue.Signed-off-by: Qing He <[EMAIL PROTECTED]> Thanks, Qing
kvm-pic-apic-mutual-exclusive.patch
Description: kvm-pic-apic-mutual-exclusive.patch
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