commit 9b1a9ad955d9ac44ee6e60b4a565edf044d3dcc7
Author: root <root@vt32-pae.(none)>
Date:   Fri Aug 10 22:38:59 2007 +0800

    APIC_TMCCT is a dynamically running count which always
    need to be recalculated at the time it is read. Setting
    intermediate value is meaningless.
    
    Signed-off-by: Yaozu (Eddie) Dong <Eddie.Dong@intel.com>

diff --git a/drivers/kvm/lapic.c b/drivers/kvm/lapic.c
index d59b69f..fc53e88 100644
--- a/drivers/kvm/lapic.c
+++ b/drivers/kvm/lapic.c
@@ -445,7 +445,7 @@ static u32 apic_get_tmcct(struct kvm_lapic *apic)
 {
 	u32 counter_passed;
 	ktime_t passed, now = apic->timer.dev.base->get_time();
-	u32 tmcct = apic_get_reg(apic, APIC_TMCCT);
+	u32 tmcct = apic_get_reg(apic, APIC_TMICT);
 
 	ASSERT(apic != NULL);
 
@@ -474,9 +474,6 @@ static u32 apic_get_tmcct(struct kvm_lapic *apic)
 			} while (tmcct <= 0);
 	}
 
-	apic->timer.last_update = now;
-	apic_set_reg(apic, APIC_TMCCT, tmcct);
-
 	return tmcct;
 }
 
@@ -633,7 +630,6 @@ static void apic_mmio_write(struct kvm_io_device *this,
 			u32 offset;
 
 			apic_set_reg(apic, APIC_TMICT, val);
-			apic_set_reg(apic, APIC_TMCCT, val);
 			apic->timer.last_update = now;
 			offset =
 			    APIC_BUS_CYCLE_NS * apic->timer.divide_count * val;
@@ -815,7 +811,6 @@ static void lapic_reset(struct kvm_vcpu *vcpu)
 	apic_set_reg(apic, APIC_ICR2, 0);
 	apic_set_reg(apic, APIC_TDCR, 0);
 	apic_set_reg(apic, APIC_TMICT, 0);
-	apic_set_reg(apic, APIC_TMCCT, 0);
 	for (i = 0; i < 8; i++) {
 		apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 		apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
@@ -886,13 +881,10 @@ static int __apic_timer_fn(struct kvm_lapic *apic)
 		u32 offset;
 		u32 tmict = apic_get_reg(apic, APIC_TMICT);
 
-		apic_set_reg(apic, APIC_TMCCT, tmict);
 		offset = APIC_BUS_CYCLE_NS * apic->timer.divide_count * tmict;
 
 		result = 1;
 		apic->timer.dev.expires = ktime_add_ns(now, offset);
-	} else {
-		apic_set_reg(apic, APIC_TMCCT, 0);
 	}
 
 	return result;
@@ -996,7 +988,6 @@ void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
 			     MSR_IA32_APICBASE_BASE;
 	apic_set_reg(apic, APIC_LVR, APIC_VERSION);
 	val = apic_get_reg(apic, APIC_TMICT);
-	apic_set_reg(apic, APIC_TMCCT, val);
 	apic_update_ppr(apic);
 
  	/* TODO: following code can be in a common API */