Guido Guenther wrote:
> Hi Avi,
> On Thu, Jan 03, 2008 at 11:17:50PM +0200, Avi Kivity wrote:
>
>> While pci interrupts are documented as active high, the documentation for
>> the piix4 pic elcr registers suggests piix4 level-triggered interrupts are
>> active high. So there is some inconsistency somewhere involving qemu
>> interrupt generation (which IIRC treats all interrupts as active high), the
>> ioapic (qemu doesn't implement polarity), bios setup, and the acpi dsdt.
>>
> We currently specify INT10 as active high in the dsl so I added an
> override entry to the madt an now the OS knows about it and things work
> as expected - we this be o.k. until all the IRQ setup gets a revamp:
>
> >From 7950892de473d42ce57e0727594190b4bfafab14 Mon Sep 17 00:00:00 2001
> From: Guido Guenther <[EMAIL PROTECTED]>
> Date: Fri, 4 Jan 2008 19:26:33 +0100
> Subject: [PATCH] int 10 is currently active high
>
> so add a proper interrupt override entry to the MADT so the OS knows about it.
> Fixes the ACPI powerbutton and should also fix the PM timer.
>
Since it is the OS that assigns SCI to irq10, we can't be sure it will
always be there. So I think all PCI IRQs need such an override.
Also, does this work if you remove the sci hack in piix3_set_irq()
piix3_dev->config[0x60 + irq_num] &= ~0x80; // enable bit
?
--
error compiling committee.c: too many arguments to function
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