On Wed, Feb 13, 2008 at 11:50:58AM +0200, Avi Kivity wrote:
> Joerg Roedel wrote:
> >@@ -1224,6 +1261,15 @@ static int svm_set_msr(struct kvm_vcpu *vcpu,
> >unsigned ecx, u64 data)
> > if (data != 0)
> > goto unhandled;
> > break;
> >+ case MSR_IA32_DEBUGCTLMSR:
> >+ svm->vmcb->save.dbgctl = data;
> >+ if (!svm_has(SVM_FEATURE_LBRV))
> >+ break;
> >+ if (data & (1ULL<<0))
> >+ svm_enable_lbrv(svm);
> >+ else
> >+ svm_disable_lbrv(svm);
> >+ break;
> > default:
> > unhandled:
> > return kvm_set_msr_common(vcpu, ecx, data);
> >
>
> This still has the same issue as the previous patchset: if the guest enables
> some other bit
> in MSR_IA32_DEBUCTLMSR, we silently ignore it. We should either pr_unimpl()
> on such bits or
> not handle them (ultimately injecting a #GP).
Thats not true. The patch saves the MSR value in vmcb->save.dbgctl. This
value is returned on reads of that MSR. So no bit is ignored. This value
in the VMCB is also used as the guests copy of that MSR if LBR
virtualization is enabled. But another issue, I should ensure the guest
does not set reserved bits in that MSR.
> Also, I'd like a simple patch for 2.6.25 to add support for Windows x86 on
> AMD. So if the
> first patch in the series can add support for the bits that Windows sets in
> MSR_IA32_DEBUGCTLMSR (I imagine it just writes zero?) then I can queue that
> for 2.6.25 and
> the rest for 2.6.26.
Ok, I will work that into the patchset.
Joerg
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