Blue Swirl wrote:
> On 3/30/08, Anthony Liguori <[EMAIL PROTECTED]> wrote:
>   
>> Blue Swirl wrote:
>>  > On 3/30/08, Anthony Liguori <[EMAIL PROTECTED]> wrote:
>>  >
>>  >> This patch introduces a PCI DMA API and some generic code to support 
>> other DMA
>>  >>  APIs.  Two types are introduced: PhysIOVector and IOVector.  A DMA API
>>  >>  maps a PhysIOVector, which is composed of target_phys_addr_t, into an 
>> IOVector,
>>  >>  which is composed of void *.
>>  >>
>>  >
>>  > This looks like it wouldn't scale to handle the Sparc systems. There
>>  > we want to make more translation steps from DVMA addresses to physical
>>  > in DMA controller and IOMMU and only in the final stage to void *. To
>>  > handle this, probably there should be an opaque parameter and some way
>>  > to register the translation function. Otherwise the API looks OK.
>>  >
>>
>>
>> I think having the PCI DMA API translate PhysIOVector => PhysIOVector
>>  would help.  Then it becomes pretty easy to just call the DMA controller
>>  for additional translation from the IOMMU.
>>
>>  Does that sound right?  I don't quite understand what role the opaque
>>  parameter would serve.
>>     
>
> Devices should not need to know about the underlying buses, so they
> can be used in different systems.

I don't think it will be too hard for a device to support multiple buses 
if we have the DMA API at the bus level.  In the future, the per-bus DMA 
API may have slight, but important differences.  For instance, at some 
point, PCI devices will be capable of recovering from an IO fault and 
you'd eventually want the DMA API to reflect this for PCI.

Regards,

Anthony LIguori

>  So the translators just call
> recursively next ones until we get physical memory. I would use the
> opaque parameter as a pointer to each translator's own state
> structures. But if you can implement this without the parameter,
> great!
>   


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