If HDEC expires when interrupts are off, the HDEC interrupt stays
pending until interrupts get re-enabled. I'm not sure exactly what
the conditions are that cause an HDEC interrupt to get lost, but they
seem to involve at least a partition switch.
On some CPUs, if the top bit of the decrementer is 0 again when you
re-enable
the interrupt, the interrupt is lost (so it is actually
level-triggered).
The arch books talk a bit about this AFAIR.
Sure, but that shouldn't happen with HDEC during the odd 50
instructions that it takes to enter the guest :)
It's more like 500 insns, including some ptesync, so lots of cycles too.
Can another hardware thread be running at the same time?
Segher
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