Alexander Graf <[email protected]> writes:
> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
>> Although it's optional IBM POWER cpus always had DAR value set on
>> alignment interrupt. So don't try to compute these values.
>>
>> Signed-off-by: Aneesh Kumar K.V <[email protected]>
>> ---
>> Changes from V3:
>> * Use make_dsisr instead of checking feature flag to decide whether to use
>> saved dsisr or not
>>
....
>> ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst)
>> {
>> +#ifdef CONFIG_PPC_BOOK3S_64
>> + return vcpu->arch.fault_dar;
>
> How about PA6T and G5s?
>
>
Paul mentioned that BOOK3S always had DAR value set on alignment
interrupt. And the patch is to enable/collect correct DAR value when
running with Little Endian PR guest. Now to limit the impact and to
enable Little Endian PR guest, I ended up doing the conditional code
only for book3s 64 for which we know for sure that we set DAR value.
-aneesh
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