On 17.06.14 10:37, Alexander Graf wrote:
On 17.06.14 03:02, Paul Mackerras wrote:
On Wed, Jun 11, 2014 at 12:33:50PM +0200, Alexander Graf wrote:
On the exit path from the guest we check what type of interrupt we
received
if we received one. This means we're doing hardware access to the
XICS interrupt
controller.
However, when running on a little endian system, this access is byte
reversed.
So let's make sure to swizzle the bytes back again and virtuall make
XICS
accesses big endian.
...
@@ -2241,7 +2253,8 @@ kvmppc_read_intr:
42: /* It's not an IPI and it's for the host, stash it in the PACA
* before exit, it will be picked up by the host ICP driver
*/
- stw r0, HSTATE_SAVED_XIRR(r13)
+ li r4, HSTATE_SAVED_XIRR
+ STWX_BE r0, r13, r4
This is a paca field, not something mandated by PAPR or shared with
the guest, so why do we need to keep it BE? If you do make it BE,
don't you also need to fix kvmppc_get_xics_latch()?
Yikes. Yes. Thanks a lot for the catch!
Eh, no. What we do is we read (good on BE, byte reversed) into r0. Then
we swab32() from r0 to r3 on LE, mr from r0 to r3 on BE.
r3 gets truncated along the way.
The reason we maintain r0 as wrong-endian is that we write it back using
the cache inhibited stwcix instruction:
stwcix r0, r6, r7 /* EOI it */
So during the lifetime of r0 as XIRR it's always byte-reversed on LE.
That's why we store it using STWX_BE into hstate, because that's the
time when we actually swab32() it for further interpretation.
Alternatively I could clobber a different register and maintain the byte
swapped variant in there if you prefer.
Alex
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