Hi Alex,
On Tue, Jun 24, 2008 at 07:04:45AM +0200, Alexander Graf wrote:
> Netware writes and reads to the DEBUGCTL and LAST*IP MSRs without
> further checks and is really confused to receive a #GP during that. To
> make it happy we should just make them stubs, which is exactly what
> SVM already does.
>
> To support VMX too, I put these in the generic code. Maybe the SVM
> code could be cleaned up to use generic code too.
I would prefer if you put that into the VMX specific code. We can't move
the SVM parts of it into generic code because Barcelona has hardware
support to virtualize these registers. Therefore SVM don't need that
in generic code.
> Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
>
>
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index fc0721e..02f8490 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -609,6 +609,11 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr,
> u64 data)
> pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
> __func__, data);
> break;
> + case MSR_IA32_DEBUGCTLMSR:
> + case MSR_IA32_LASTBRANCHFROMIP:
> + case MSR_IA32_LASTBRANCHTOIP:
> + case MSR_IA32_LASTINTFROMIP:
> + case MSR_IA32_LASTINTTOIP:
> case MSR_IA32_UCODE_REV:
> case MSR_IA32_UCODE_WRITE:
> break;
> @@ -705,6 +710,11 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr,
> u64 *pdata)
> case MSR_IA32_MC0_MISC+16:
> case MSR_IA32_UCODE_REV:
> case MSR_IA32_EBL_CR_POWERON:
> + case MSR_IA32_DEBUGCTLMSR:
> + case MSR_IA32_LASTBRANCHFROMIP:
> + case MSR_IA32_LASTBRANCHTOIP:
> + case MSR_IA32_LASTINTFROMIP:
> + case MSR_IA32_LASTINTTOIP:
> data = 0;
> break;
> case MSR_MTRRcap:
--
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