I've been playing with my hpet patch on kvm and seeing some strange
behavior. The patch I've been using is attached below.
/usr/local/bin/qemu-system-x86_64 -boot cd -hda
/home/beth/images/ubuntu_server_8.04_10G.img -m 1024 -net nic,model=e1000 -net
user -smp 2 -vnc :1
With the above command line the boot intermittently fails with an infinite
roll of error messages that look something like this:
*********************BEGIN ERROR MESSAGES********************************
...
ACPI Exception (evgpe-0704): AE_NO_MEMORY, Unable to queue handler for GPE[ E]
- event disabled [20070126]
ACPI Exception (evgpe-0704): AE_NO_MEMORY, Unable to queue handler for GPE[ F]
- event disabled [20070126]
printk: 242 messages suppressed.
kacpid: page allocation failure. order:0, mode:0x20
Pid: 93, comm: kacpid Not tainted 2.6.25.9 #13
Call Trace:
<IRQ> [<ffffffff8025f143>] __alloc_pages+0x325/0x33e
[<ffffffff8027b27c>] kmem_getpages+0xc6/0x194
[<ffffffff8027b85a>] fallback_alloc+0x10d/0x185
[<ffffffff8027bea7>] kmem_cache_alloc+0xbd/0xe7
[<ffffffff80369944>] acpi_ev_asynch_execute_gpe_method+0x0/0x117
[<ffffffff80362e9f>] acpi_os_execute+0x2e/0x9a
[<ffffffff80369823>] acpi_ev_gpe_dispatch+0xd0/0x149
[<ffffffff80369b0c>] acpi_ev_gpe_detect+0xb1/0x104
[<ffffffff80367600>] acpi_ev_fixed_event_detect+0x34/0xd4
[<ffffffff8036800a>] acpi_ev_sci_xrupt_handler+0x1a/0x22
[<ffffffff80362895>] acpi_irq+0x11/0x23
[<ffffffff802553a0>] handle_IRQ_event+0x25/0x53
[<ffffffff802567f6>] handle_fasteoi_irq+0x90/0xc8
[<ffffffff8020da12>] do_IRQ+0xf1/0x15f
[<ffffffff8020b471>] ret_from_intr+0x0/0xa
[<ffffffff80233398>] __do_softirq+0x5a/0xce
[<ffffffff8020c0ec>] call_softirq+0x1c/0x28
[<ffffffff8020d794>] do_softirq+0x2c/0x68
[<ffffffff802332fa>] irq_exit+0x3f/0x83
[<ffffffff8020da5f>] do_IRQ+0x13e/0x15f
[<ffffffff8020b471>] ret_from_intr+0x0/0xa
<EOI> [<ffffffff80371f1c>] acpi_ns_get_parent_node+0x14/0x15
[<ffffffff80371b08>] acpi_ns_delete_namespace_by_owner+0xb7/0xde
[<ffffffff80365641>] acpi_ds_terminate_control_method+0x73/0xc6
[<ffffffff80373933>] acpi_ps_parse_aml+0x179/0x254
[<ffffffff80374c4c>] acpi_ps_execute_method+0x12b/0x1d7
[<ffffffff80371c18>] acpi_ns_evaluate+0xa4/0x100
[<ffffffff80369a08>] acpi_ev_asynch_execute_gpe_method+0xc4/0x117
[<ffffffff80362dd6>] acpi_os_execute_deferred+0x0/0x2c
[<ffffffff80362df9>] acpi_os_execute_deferred+0x23/0x2c
[<ffffffff8023cb6c>] run_workqueue+0x79/0x104
[<ffffffff8023d47f>] worker_thread+0xd9/0xe8
[<ffffffff8023fc91>] autoremove_wake_function+0x0/0x2e
[<ffffffff8023d3a6>] worker_thread+0x0/0xe8
[<ffffffff8023fb5d>] kthread+0x47/0x76
[<ffffffff80229e74>] schedule_tail+0x28/0x5c
[<ffffffff8020bd78>] child_rip+0xa/0x12
[<ffffffff8023fb16>] kthread+0x0/0x76
[<ffffffff8020bd6e>] child_rip+0x0/0x12
Mem-info:
Node 0 DMA per-cpu:
CPU 0: hi: 0, btch: 1 usd: 0
CPU 1: hi: 0, btch: 1 usd: 0
Node 0 DMA32 per-cpu:
CPU 0: hi: 186, btch: 31 usd: 65
CPU 1: hi: 186, btch: 31 usd: 184
Active:0 inactive:0 dirty:0 writeback:0 unstable:0
free:0 slab:255796 mapped:0 pagetables:0 bounce:0
Node 0 DMA free:0kB min:0kB low:0kB high:0kB active:0kB inactive:0kB
present:8924kB pages_scanned:0 all_unreclaimable? no
lowmem_reserve[]: 0 0 0 0
Node 0 DMA32 free:0kB min:0kB low:0kB high:0kB active:0kB inactive:0kB
present:1018020kB pages_scanned:0 all_unreclaimable? no
lowmem_reserve[]: 0 0 0 0
Node 0 DMA: 0*4kB 0*8kB 0*16kB 0*32kB 0*64kB 0*128kB 0*256kB 0*512kB 0*1024kB
0*2048kB 0*4096kB = 0kB
Node 0 DMA32: 0*4kB 0*8kB 0*16kB 0*32kB 0*64kB 0*128kB 0*256kB 0*512kB 0*1024kB
0*2048kB 0*4096kB = 0kB
0 total pagecache pages
Swap cache: add 0, delete 0, find 0/0
Free swap = 0kB
Total swap = 0kB
Free swap: 0kB
262128 pages of RAM
5637 reserved pages
0 pages shared
0 pages swap cached
ACPI Exception (evgpe-0704): AE_NO_MEMORY, Unable to queue handler for GPE[ 8]
- event disabled [20070126]
ACPI Exception (evgpe-0704): AE_NO_MEMORY, Unable to queue handler for GPE[ 9]
- event disabled [20070126]
...
*************END ERROR MESSAGES******************************************
If I add -no-kvm-irqchip, the error disappears.
Can anyone offer any insight about what is going on here? I don't know if it
is related, but booting linux with the hpet seems to stall in some places, and
I don't see that when booting without the hpet.
Other than this problem, I have booted win2k8 and linux with the hpet. The
only other odd situation is that, to get linux to work I
have to use irq 0 for timer0, but to get windows to work, I have to
use irq 2. In hpet.c update_irq:
if (timer->tn == 0)
irq=timer->state->irqs[0];
must be changed to
if (timer->tn == 0)
irq=timer->state->irqs[2];
to get win2k8 to boot.
Any ideas?
Beth Kon
IBM Linux Technology Center
**************************************
signed-off-by Beth Kon <[EMAIL PROTECTED]>
diff --git a/qemu/Makefile.target b/qemu/Makefile.target
index a86464f..8634186 100644
--- a/qemu/Makefile.target
+++ b/qemu/Makefile.target
@@ -607,7 +607,7 @@ ifeq ($(TARGET_BASE_ARCH), i386)
OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o
OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
OBJS+= cirrus_vga.o apic.o parallel.o acpi.o piix_pci.o
-OBJS+= usb-uhci.o vmmouse.o vmport.o vmware_vga.o extboot.o
+OBJS+= usb-uhci.o vmmouse.o vmport.o vmware_vga.o extboot.o hpet.o
ifeq ($(USE_KVM_PIT), 1)
OBJS+= i8254-kvm.o
endif
diff --git a/qemu/hw/hpet.c b/qemu/hw/hpet.c
new file mode 100644
index 0000000..01dee56
--- /dev/null
+++ b/qemu/hw/hpet.c
@@ -0,0 +1,486 @@
+/*
+ * High Precisition Event Timer emulation
+ *
+ * Copyright (c) 2007 Alexander Graf
+ * Copyright (c) 2008 IBM Corporation
+ *
+ * Authors: Beth Kon <[EMAIL PROTECTED]>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * *****************************************************************
+ *
+ * This driver attempts to emulate an HPET device in software. It is by no
+ * means complete and is prone to break on certain conditions.
+ *
+ */
+#include "hw.h"
+#include "console.h"
+#include "qemu-timer.h"
+
+//#define HPET_DEBUG
+
+#define HPET_BASE 0xfed00000
+#define HPET_CLK_PERIOD 10000000ULL /* 10000000 femtoseconds == 10ns*/
+
+#define FS_PER_NS 1000000
+#define HPET_NUM_TIMERS 3
+#define HPET_TIMER_TYPE_LEVEL 1
+#define HPET_TIMER_TYPE_EDGE 0
+#define HPET_TIMER_DELIVERY_APIC 0
+#define HPET_TIMER_DELIVERY_FSB 1
+#define HPET_TIMER_CAP_FSB_INT_DEL (1 << 15)
+#define HPET_TIMER_CAP_PER_INT (1 << 4)
+
+#define HPET_CFG_ENABLE 0x001
+#define HPET_CFG_LEGACY 0x002
+
+#define HPET_ID 0x000
+#define HPET_PERIOD 0x004
+#define HPET_CFG 0x010
+#define HPET_STATUS 0x020
+#define HPET_COUNTER 0x0f0
+#define HPET_TN_REGS 0x100 ... 0x3ff /*address range of all TN regs*/
+#define HPET_TN_CFG 0x000
+#define HPET_TN_CMP 0x008
+#define HPET_TN_ROUTE 0x010
+
+
+#define HPET_TN_INT_TYPE_LEVEL 0x002
+#define HPET_TN_ENABLE 0x004
+#define HPET_TN_PERIODIC 0x008
+#define HPET_TN_PERIODIC_CAP 0x010
+#define HPET_TN_SIZE_CAP 0x020
+#define HPET_TN_SETVAL 0x040
+#define HPET_TN_32BIT 0x100
+#define HPET_TN_INT_ROUTE_MASK 0x3e00
+#define HPET_TN_INT_ROUTE_SHIFT 9
+#define HPET_TN_INT_ROUTE_CAP_SHIFT 32
+#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
+
+#define timer_int_route(timer) \
+ ((timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT)
+
+#define hpet_enabled(s) (s->config & HPET_CFG_ENABLE)
+#define timer_is_periodic(t) (t->config & HPET_TN_PERIODIC)
+#define timer_enabled(t) (t->config & HPET_TN_ENABLE)
+
+struct HPETState;
+typedef struct HPETTimer { /* timers */
+ uint8_t tn; /*timer number*/
+ QEMUTimer *qemu_timer;
+ struct HPETState *state;
+ /* Memory-mapped, software visible timer registers */
+ uint64_t config; /* configuration/cap */
+ uint64_t cmp; /* comparator */
+ uint64_t fsb; /* FSB route, not supported now */
+ /* Hidden register state */
+ uint64_t period; /* Last value written to comparator */
+} HPETTimer;
+
+
+typedef struct HPETState {
+ uint64_t hpet_offset;
+ qemu_irq *irqs;
+ HPETTimer timer[HPET_NUM_TIMERS];
+ /* Memory-mapped, software visible registers */
+ uint64_t capability; /* capabilities */
+ uint64_t config; /* configuration */
+ uint64_t isr; /* interrupt status reg */
+ uint64_t hpet_counter; /* main counter */
+} HPETState;
+
+
+
+int hpet_legacy=0;
+
+static void update_irq(struct HPETTimer *timer)
+{
+ qemu_irq irq;
+ int route;
+
+ if ( (timer->tn <= 1) && (timer->state->config & HPET_CFG_LEGACY) ) {
+
+ /* if LegacyReplacementRoute bit is set, HPET specification requires
+ * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
+ * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
+ */
+ if (timer->tn == 0)
+ irq=timer->state->irqs[0];
+ else
+ irq=timer->state->irqs[8];
+ }else{
+ route=timer_int_route(timer);
+ irq=timer->state->irqs[route];
+ }
+
+ if(timer_enabled(timer) && hpet_enabled(timer->state)) {
+ qemu_irq_pulse(irq);
+ }
+}
+
+static inline uint64_t ticks_to_ns(uint64_t value)
+{
+ return (value * HPET_CLK_PERIOD / FS_PER_NS);
+}
+
+static inline uint64_t ns_to_ticks(uint64_t value)
+{
+ return (value * FS_PER_NS / HPET_CLK_PERIOD);
+}
+
+static inline uint64_t hpet_fixup_reg(
+ uint64_t new, uint64_t old, uint64_t mask)
+{
+ new &= mask;
+ new |= old & ~mask;
+ return new;
+}
+
+/* .97656 ms */
+#define HPET_TINY_TIME_SPAN (HPET_PERIOD * 97656)
+static uint64_t calculate_diff(uint64_t cmp, uint64_t current, HPETTimer *t)
+{
+
+ uint64_t diff;
+ diff = cmp - current;
+
+ /*
+ * Detect time values set in the past. This is hard to do for 32-bit
+ * comparators as the timer does not have to be set that far in the future
+ * for the counter difference to wrap a 32-bit signed integer. We fudge
+ * by looking for a 'small' time value in the past.
+ */
+ if ((int64_t)diff < 0)
+ diff = ((t->config & HPET_TN_32BIT) && (-diff > HPET_TINY_TIME_SPAN))
+ ? (uint32_t)diff : 0;
+ return diff;
+}
+
+static void hpet_timer(void *opaque)
+{
+ HPETTimer *t = (HPETTimer*)opaque;
+ uint64_t diff;
+
+ if (timer_is_periodic(t) && (t->period != 0))
+ {
+ uint64_t cur_tick = ns_to_ticks(qemu_get_clock(vm_clock));
+ uint64_t period = t->period;
+ if (t->config & HPET_TN_32BIT) {
+ t->cmp = (uint32_t)(t->cmp + period);
+ cur_tick = (uint32_t)cur_tick;
+ } else
+ t->cmp += period;
+ diff = calculate_diff(t->cmp, cur_tick, t);
+ qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
+ + ticks_to_ns(diff));
+ }
+
+ update_irq(t);
+}
+
+static void hpet_set_timer(HPETTimer *t)
+{
+ uint64_t diff, cmp, cur_tick;
+
+ cur_tick = ns_to_ticks(qemu_get_clock(vm_clock));
+ cmp = t->cmp;
+ if (t->config & HPET_TN_32BIT) {
+ cmp = (uint32_t)cmp;
+ cur_tick = (uint32_t)cur_tick;
+ }
+ diff = calculate_diff(cmp, cur_tick, t);
+
+ qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) +
ticks_to_ns(diff));
+}
+
+static void hpet_del_timer(HPETTimer *t)
+{
+ qemu_del_timer(t->qemu_timer);
+}
+static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
+{
+#ifdef HPET_DEBUG
+ fprintf(stderr, "qemu: hpet_read b at %" PRIx64 "\n", addr);
+#endif
+ return 10;
+}
+
+static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
+{
+#ifdef HPET_DEBUG
+ fprintf(stderr, "qemu: hpet_read w at %" PRIx64 "\n", addr);
+#endif
+ return 10;
+}
+
+static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
+{
+ HPETState *s = (HPETState *)opaque;
+ uint64_t cur_tick;
+#ifdef HPET_DEBUG
+ fprintf(stderr, "qemu: hpet_read l at %" PRIx64 "\n", addr);
+#endif
+ switch(addr - HPET_BASE) {
+ case HPET_ID:
+ return s->capability;
+ case HPET_PERIOD:
+ return s->capability >> 32;
+ case HPET_CFG:
+ return s->config;
+ case HPET_CFG + 4:
+#ifdef HPET_DEBUG
+ fprintf(stderr, "qemu: invalid hpet_read l at %" PRIx64 "\n",
addr);
+#endif
+ return 0;
+ case HPET_COUNTER:
+ if (hpet_enabled(s))
+ cur_tick = ns_to_ticks(qemu_get_clock(vm_clock)
+ - s->hpet_offset) ;
+ else
+ cur_tick = s->hpet_counter;
+#ifdef HPET_DEBUG
+ fprintf(stderr, "qemu: reading counter %" PRIx64 "\n", cur_tick);
+#endif
+ return cur_tick;
+ case HPET_COUNTER + 4:
+ return 0;
+ case HPET_STATUS:
+ return s->isr;
+ case HPET_TN_REGS:
+ {
+ uint8_t timer_id = (addr - HPET_BASE - 0x100) / 0x20;
+ if (timer_id > HPET_NUM_TIMERS - 1) {
+ fprintf(stderr, "qemu: timer id out of range\n");
+ return 0;
+ }
+ HPETTimer *timer = &s->timer[timer_id];
+
+ switch((addr - HPET_BASE - 0x100) % 0x20) {
+ case HPET_TN_CFG:
+ return timer->config;
+ case HPET_TN_CFG + 4: // Interrupt capabilities
+ return timer->config >> 32;
+ case HPET_TN_CMP: // comparator register
+ return timer->cmp;
+ case HPET_TN_CMP + 4:
+ return timer->cmp >> 32;
+ case HPET_TN_ROUTE:
+ return timer->fsb >> 32;
+ }
+ }
+ break;
+ }
+
+#ifdef HPET_DEBUG
+ fprintf(stderr, "qemu: invalid hpet_read l at %" PRIx64 "\n", addr);
+#endif
+ return 10;
+}
+
+static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+#ifdef HPET_DEBUG
+ fprintf(stderr, "qemu: invalid hpet_write b at %" PRIx64 " = %#x\n", addr,
value);
+#endif
+}
+
+static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+#ifdef HPET_DEBUG
+ fprintf(stderr, "qemu: invalid hpet_write w at %" PRIx64 " = %#x\n", addr,
value);
+#endif
+}
+
+static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ int i;
+ HPETState *s = (HPETState *)opaque;
+ uint64_t old_val, new_val;
+
+#ifdef HPET_DEBUG
+ fprintf(stderr, "qemu: hpet_write l at %" PRIx64 " = %#x\n", addr, value);
+#endif
+ old_val = hpet_ram_readl(opaque, addr);
+ new_val = value;
+
+
+ switch(addr - HPET_BASE) {
+ case HPET_ID:
+ return;
+ case HPET_CFG:
+ s->config = hpet_fixup_reg(new_val, old_val, 0x3);
+ if (!(old_val & HPET_CFG_ENABLE) && (new_val & HPET_CFG_ENABLE)) {
+ /* Enable main counter and interrupt generation. */
+ s->hpet_offset = qemu_get_clock(vm_clock)
+ - ticks_to_ns(s->hpet_counter);
+ for (i = 0; i < HPET_NUM_TIMERS; i++)
+ hpet_set_timer(&s->timer[i]);
+ }
+ else if ( (old_val & HPET_CFG_ENABLE) &&
+ !(new_val & HPET_CFG_ENABLE)) {
+ /* Halt main counter and disable interrupt generation. */
+ s->hpet_counter = ns_to_ticks(qemu_get_clock(vm_clock)
+ - s->hpet_offset) ;
+ for (i = 0; i < HPET_NUM_TIMERS; i++)
+ hpet_del_timer(&s->timer[i]);
+ }
+ hpet_legacy = s->config & HPET_CFG_LEGACY;
+ break;
+ case HPET_CFG + 4:
+#ifdef HPET_DEBUG
+ fprintf(stderr, "qemu: invalid hpet_write l at %" PRIx64 " =
%#x\n", addr,
+ value);
+#endif
+ break;
+ case HPET_STATUS:
+ /* FIXME: need to handle level-triggered interrupts */
+ break;
+ case HPET_COUNTER:
+
+ if (hpet_enabled(s))
+ fprintf(stderr, "qemu: Writing counter while HPET enabled!\n");
+ s->hpet_counter = value;
+ break;
+ case HPET_COUNTER + 4:
+ s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
+ | (((uint64_t)value) << 32);
+#ifdef HPET_DEBUG
+ fprintf(stderr, "qemu: HPET counter 0xf4 set to %#x -> %" PRIx64
"\n",
+ value, s->hpet_counter);
+#endif
+ break;
+ case HPET_TN_REGS:
+ {
+ uint8_t timer_id = (addr - HPET_BASE - 0x100) / 0x20;
+#ifdef HPET_DEBUG
+ fprintf(stderr,
+ "qemu: hpet_write l timer_id = %#x \n",
+ timer_id);
+#endif
+ HPETTimer *timer = &s->timer[timer_id];
+
+ switch((addr - HPET_BASE - 0x100) % 0x20) {
+ case HPET_TN_CFG:
+#ifdef HPET_DEBUG
+ fprintf(stderr,
+ "qemu: hpet_write l TN config value
%#x\n",
+ value);
+#endif
+ timer->config =
+ hpet_fixup_reg(new_val, old_val, 0x3f4e);
+ if (new_val & HPET_TN_32BIT) {
+ timer->cmp = (uint32_t)timer->cmp;
+ timer->period = (uint32_t)timer->period;
+ }
+ if (new_val & HPET_TIMER_TYPE_LEVEL){
+ fprintf(stderr,
+ "qemu: level-triggered hpet not supported\n");
+ exit (-1);
+ }
+
+ break;
+#ifdef HPET_DEBUG
+ case HPET_TN_CFG + 4: // Interrupt capabilities
+ fprintf(stderr,
+ "qemu: invalid hpet_write l at %" PRIx64 "
= %#x\n",
+ addr, value);
+ break;
+#endif
+ case HPET_TN_CMP: // comparator register
+#ifdef HPET_DEBUG
+ fprintf(stderr,
+ "qemu: hpet_write l TN comparator value
%#x\n",
+ value);
+#endif
+ if ( timer->config & HPET_TN_32BIT)
+ new_val = (uint32_t)new_val;
+ if ( !timer_is_periodic(timer) ||
+ (timer->config & HPET_TN_SETVAL) )
+ timer->cmp = new_val;
+ else {
+ /*
+ * FIXME: Clamp period to reasonable min/max
values:
+ */
+ timer->period = new_val;
+ }
+ timer->config &= ~HPET_TN_SETVAL;
+ if ( hpet_enabled(s) )
+ hpet_set_timer(timer);
+ break;
+
+ case HPET_TN_ROUTE + 4:
+#ifdef HPET_DEBUG
+ fprintf(stderr,
+ "qemu: invalid hpet_write l at %" PRIx64 "
= %#x\n",
+ addr, value);
+#endif
+ break;
+ }
+ }
+ break;
+ default:
+ fprintf(stderr, "qemu: invalid hpet_write l at %" PRIx64 " =
%#x\n",
+ addr, value);
+ }
+
+}
+
+static CPUReadMemoryFunc *hpet_ram_read[] = {
+ hpet_ram_readb,
+ hpet_ram_readw,
+ hpet_ram_readl,
+};
+
+static CPUWriteMemoryFunc *hpet_ram_write[] = {
+ hpet_ram_writeb,
+ hpet_ram_writew,
+ hpet_ram_writel,
+};
+
+
+void hpet_init(qemu_irq *irq) {
+ int iomemtype, i;
+ HPETState *s;
+
+ /* XXX this is a dirty hack for HPET support w/o LPC
+ Actually this is a config descriptor for the RCBA */
+ fprintf (stderr, "hpet_init\n");
+ s = qemu_mallocz(sizeof(HPETState));
+ s->irqs = irq;
+ /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
+ s->capability = 0x8086A201ULL;
+ s->capability |= ((HPET_CLK_PERIOD) << 32);
+
+ for(i=0; i<HPET_NUM_TIMERS; i++) {
+ HPETTimer *timer = &s->timer[i];
+ timer->tn = i;
+ timer->cmp = ~0ULL;
+ timer->config = HPET_TN_PERIODIC_CAP;
+ timer->config |= 0x00ffULL << 32;
+ timer->state = s;
+ timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
+ }
+
+ /* HPET Area */
+
+ iomemtype = cpu_register_io_memory(0, hpet_ram_read,
+ hpet_ram_write, s);
+
+ cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
+}
diff --git a/qemu/hw/i8254.c b/qemu/hw/i8254.c
index 69eb889..452dcee 100644
--- a/qemu/hw/i8254.c
+++ b/qemu/hw/i8254.c
@@ -27,6 +27,10 @@
#include "qemu-timer.h"
#include "i8254.h"
+#if defined TARGET_I386 || defined TARGET_X86_64
+extern int hpet_legacy;
+#endif
+
//#define DEBUG_PIT
static PITState pit_state;
@@ -344,9 +348,15 @@ static void pit_irq_timer_update(PITChannelState *s,
int64_t current_time)
if (!s->irq_timer)
return;
+#if defined TARGET_I386 || defined TARGET_X86_64
+ if (hpet_legacy) {
+ qemu_del_timer(s->irq_timer);
+ return;
+ }
+#endif
expire_time = pit_get_next_transition_time(s, current_time);
irq_level = pit_get_out1(s, current_time);
- qemu_set_irq(s->irq, irq_level);
+ qemu_set_irq(s->irq, irq_level);
if (time_drift_fix && irq_level==1) {
/* FIXME: fine tune timer_max_fix (max fix per tick).
* Should it be 1 (double time), 2 , 4, 10 ?
diff --git a/qemu/hw/mc146818rtc.c b/qemu/hw/mc146818rtc.c
index 30bb044..3b6157e 100644
--- a/qemu/hw/mc146818rtc.c
+++ b/qemu/hw/mc146818rtc.c
@@ -27,6 +27,9 @@
#include "pc.h"
#include "isa.h"
+#if defined TARGET_I386 || defined TARGET_X86_64
+extern int hpet_legacy;
+#endif
//#define DEBUG_CMOS
#define RTC_SECONDS 0
@@ -80,7 +83,11 @@ static void rtc_timer_update(RTCState *s, int64_t
current_time)
period_code = s->cmos_data[RTC_REG_A] & 0x0f;
if (period_code != 0 &&
+#if defined TARGET_I386 || defined TARGET_X86_64
+ (s->cmos_data[RTC_REG_B] & REG_B_PIE) && !hpet_legacy) {
+#else
(s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
+#endif
if (period_code <= 2)
period_code += 7;
/* period in 32 Khz cycles */
@@ -101,7 +108,10 @@ static void rtc_periodic_timer(void *opaque)
rtc_timer_update(s, s->next_periodic_time);
s->cmos_data[RTC_REG_C] |= 0xc0;
- qemu_irq_raise(s->irq);
+#if defined TARGET_I386 || defined TARGET_X86_64
+ if (!hpet_legacy)
+#endif
+ qemu_irq_raise(s->irq);
}
static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
@@ -281,6 +291,12 @@ static void rtc_update_second(void *opaque)
RTCState *s = opaque;
int64_t delay;
+#if defined TARGET_I386 || defined TARGET_X86_64
+ if (hpet_legacy) {
+ qemu_del_timer(s->second_timer2);
+ return;
+ }
+#endif
/* if the oscillator is not in normal operation, we do not update */
if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
s->next_second_time += ticks_per_sec;
@@ -306,6 +322,12 @@ static void rtc_update_second2(void *opaque)
{
RTCState *s = opaque;
+#if defined TARGET_I386 || defined TARGET_X86_64
+ if (hpet_legacy) {
+ qemu_del_timer(s->second_timer);
+ return;
+ }
+#endif
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
rtc_copy_date(s);
}
@@ -359,7 +381,10 @@ static uint32_t cmos_ioport_read(void *opaque, uint32_t
addr)
break;
case RTC_REG_C:
ret = s->cmos_data[s->cmos_index];
- qemu_irq_lower(s->irq);
+#if defined TARGET_I386 || defined TARGET_X86_64
+ if (!hpet_legacy)
+#endif
+ qemu_irq_lower(s->irq);
s->cmos_data[RTC_REG_C] = 0x00;
break;
default:
diff --git a/qemu/hw/pc.c b/qemu/hw/pc.c
index 3a8269b..385361f 100644
--- a/qemu/hw/pc.c
+++ b/qemu/hw/pc.c
@@ -50,6 +50,8 @@
#define MAX_IDE_BUS 2
+void hpet_init(qemu_irq irq);
+
static fdctrl_t *floppy_controller;
static RTCState *rtc_state;
static PITState *pit;
@@ -1016,6 +1018,7 @@ static void pc_init1(ram_addr_t ram_size, int
vga_ram_size,
#endif
pit = pit_init(0x40, i8259[0]);
pcspk_init(pit);
+ hpet_init(i8259);
if (pci_enabled) {
pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
}
--
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