Index: qemu/hw/apic.c
===================================================================
--- qemu.orig/hw/apic.c	2008-11-01 16:03:38.000000000 +0000
+++ qemu/hw/apic.c	2008-11-01 16:09:55.000000000 +0000
@@ -67,7 +67,6 @@
 #define MAX_APIC_WORDS 8
 
 typedef struct APICState {
-    CPUState *cpu_env;
     uint32_t apicbase;
     uint8_t id;
     uint8_t arb_id;
@@ -304,6 +303,12 @@
     return s->tpr >> 4;
 }
 
+uint8_t cpu_get_apic_id(void *opaque)
+{
+    APICState *s = opaque;
+    return s->id;
+}
+
 /* return -1 if no bit is set */
 static int get_highest_priority_int(uint32_t *tab)
 {
@@ -596,16 +601,10 @@
 
 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 {
-    CPUState *env;
-    APICState *s;
+    APICState *s = opaque;
     uint32_t val;
     int index;
 
-    env = cpu_single_env;
-    if (!env)
-        return 0;
-    s = env->apic_state;
-
     index = (addr >> 4) & 0xff;
     switch(index) {
     case 0x02: /* id */
@@ -677,15 +676,9 @@
 
 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 {
-    CPUState *env;
-    APICState *s;
+    APICState *s = opaque;
     int index;
 
-    env = cpu_single_env;
-    if (!env)
-        return;
-    s = env->apic_state;
-
 #ifdef DEBUG_APIC
     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 #endif
@@ -861,20 +854,17 @@
     apic_mem_writel,
 };
 
-int apic_init(CPUState *env, qemu_irq *cpu_SIPI, qemu_irq cpu_reset,
-              qemu_irq cpu_NMI, qemu_irq cpu_SMI, qemu_irq cpu_HWINT)
+void *apic_init(qemu_irq *cpu_SIPI, qemu_irq cpu_reset, qemu_irq cpu_NMI,
+                qemu_irq cpu_SMI, qemu_irq cpu_HWINT)
 {
     APICState *s;
 
     if (last_apic_id >= MAX_APICS)
-        return -1;
+        return NULL;
     s = qemu_mallocz(sizeof(APICState));
     if (!s)
-        return -1;
-    env->apic_state = s;
+        return s;
     s->id = last_apic_id++;
-    env->cpuid_apic_id = s->id;
-    s->cpu_env = env;
 
     s->cpu_SIPI = cpu_SIPI;
     s->cpu_reset = cpu_reset;
@@ -888,7 +878,7 @@
         /* NOTE: the APIC is directly connected to the CPU - it is not
            on the global memory bus. */
         apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
-                                                apic_mem_write, NULL);
+                                                apic_mem_write, s);
         cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
                                      apic_io_memory);
     }
@@ -898,7 +888,7 @@
     qemu_register_reset(apic_reset, s);
 
     local_apics[s->id] = s;
-    return 0;
+    return s;
 }
 
 static void ioapic_service(IOAPICState *s)
Index: qemu/hw/pc.c
===================================================================
--- qemu.orig/hw/pc.c	2008-11-01 16:05:30.000000000 +0000
+++ qemu/hw/pc.c	2008-11-01 16:11:30.000000000 +0000
@@ -827,6 +827,8 @@
     }
     
     for(i = 0; i < smp_cpus; i++) {
+        void *cpu_apic;
+
         env = cpu_init(cpu_model);
         if (!env) {
             fprintf(stderr, "Unable to find x86 CPU definition\n");
@@ -845,8 +847,11 @@
         cpu_SMIs[i] = qemu_allocate_irqs(cpu_set_SMI, env, 1);
         cpu_HWINTs[i] = qemu_allocate_irqs(cpu_set_HWINT, env, 1);
         if (pci_enabled) {
-            apic_init(env, cpu_SIPI[i], cpu_resets[i][0], cpu_NMIs[i][0],
-                      cpu_SMIs[i][0], cpu_HWINTs[i][0]);
+            cpu_apic = apic_init(cpu_SIPI[i], cpu_resets[i][0],
+                                 cpu_NMIs[i][0], cpu_SMIs[i][0],
+                                 cpu_HWINTs[i][0]);
+            env->apic_state = cpu_apic;
+            env->cpuid_apic_id = cpu_get_apic_id(cpu_apic);
         }
     }
 
Index: qemu/hw/pc.h
===================================================================
--- qemu.orig/hw/pc.h	2008-11-01 16:05:30.000000000 +0000
+++ qemu/hw/pc.h	2008-11-01 16:11:11.000000000 +0000
@@ -40,11 +40,12 @@
 /* APIC */
 typedef struct IOAPICState IOAPICState;
 
-int apic_init(CPUState *env, qemu_irq *cpu_SIPI, qemu_irq cpu_reset,
-              qemu_irq cpu_NMI, qemu_irq cpu_SMI, qemu_irq cpu_HWINT);
+void *apic_init(qemu_irq *cpu_SIPI, qemu_irq cpu_reset, qemu_irq cpu_NMI,
+                qemu_irq cpu_SMI, qemu_irq cpu_HWINT);
 int apic_accept_pic_intr(void *opaque);
 void apic_deliver_pic_intr(void *opaque, int level);
 int apic_get_interrupt(void *opaque);
+uint8_t cpu_get_apic_id(void *opaque);
 IOAPICState *ioapic_init(void);
 void ioapic_set_irq(void *opaque, int vector, int level);