The TSC is zeroed at RESET, and not at SMP initialization.
This avoids the TSC from going out of sync between vcpu's on SMP
guests.
Signed-off-by: Marcelo Tosatti <[EMAIL PROTECTED]>
Index: kvm-userspace.tip/bios/rombios32.c
===================================================================
--- kvm-userspace.tip.orig/bios/rombios32.c
+++ kvm-userspace.tip/bios/rombios32.c
@@ -610,12 +610,6 @@ void smp_probe(void)
writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
sipi_vector = AP_BOOT_ADDR >> 12;
writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
- asm volatile(
- "xor %%eax, %%eax \n\t"
- "xor %%edx, %%edx \n\t"
- "mov $0x10, %%ecx \n\t"
- "wrmsr"
- : : : "eax", "ecx", "edx");
#ifndef BX_QEMU
delay_ms(10);
Index: kvm-userspace.tip/bios/rombios32start.S
===================================================================
--- kvm-userspace.tip.orig/bios/rombios32start.S
+++ kvm-userspace.tip/bios/rombios32start.S
@@ -43,10 +43,6 @@ smp_ap_boot_code_start:
cli
xor %ax, %ax
mov %ax, %ds
- xor %eax, %eax
- xor %edx, %edx
- mov $0x10, %ecx
- wrmsr
mov $SMP_MSR_ADDR, %ebx
11:
--
--
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